Aristides (Aris) Efthymiou

School of Informatics

Informatics Forum, Room 1.11

10 Crichton Street

Edinburgh EH8 9AB

UK

Phone: +44 131 6505171

Fax: +44 131 6506899

Email:

Funding opportunities for UK/EU PhD students avalailable. Drop me an email if you are interested in computer microarchitecture, circuit design. See the list of proposed projects for computer systems.

Industrial CASE studentship in Delay fault testing of Self-timed Circuits in collaboration with Silistix Ltd. Post open to candidates from the UK only (EPSRC's rules). More details here.

Brief Biography

I am a lecturer in the Institute for Computing Systems Architecture within the School of Informatics of the University of Edinburgh. Previously I was a research associate in the APT/AMULET group at the University of Manchester, from where I received a PhD in 2003. I learned the basics of Computer Science at the CS Department of the University of Crete, where I also did an MSc by research. I had a great time back then working at the Computer Architecture and VLSI Systems (CARV) Laboratory.

Research

I am interested in the design and implementation of high-performance, energy-efficient computing systems at the micro-architecture and circuit levels. I have spent the past five years applying asynchronous design techniques to solve the problems that arise in this area but I don't believe that these techniques are suitable for every problem; the "truth" lies somewhere in between...

• Power-adaptive microarchitecture: Methods for adjusting the speed and power of a processor depending on the "computational demands" of the executing program, the available execution time, and the priorities of the system or it's user. One idea explored is pipeline collapsing: pipeline stages are split and joined while the processor is operating, effectively changing its speculation depth. Techniques for designing power-adaptive memories are considered too.
• Design for testability for asynchronous circuits: A methodology has been developed for DfT and test-pattern generation for an asynchronous interconnect. The next step is to make a substantial extension to the methodology to handle arbitrary asynchronous circuits.
• Asynchronous interconnect and interfaces: In the current and future deep-submicron technologies, the design of the on-chip interconnection network is important as a System on a Chip resembles a present-day communications network. Sun Microsystem's moto "The network is the computer" becomes literally true!
• The next big thing: fault-tolerant computing systems. It is widely anticipated that future semiconductor technologies will have low yield and produce less reliable ICs. Relaxing the fundamental assumption that every component on a chip works correctly 100% of the time will substantially improve the cost-effectiveness of ICs. The flexible timing offered by the asynchronous design style could play a signifficant role in this field as it can be used to boost the robustness of circuits.

You can find a list of my publications with links to the texts.

Current Projects

• EPSRC EP/D054400/1: Self-timed datapath synthesis - SEDATE
  In collaboration with the Universities of Manchester and Newcastle. The project investigates methods for synthesis and testing of self-timed datapaths. Edinburgh's contribution is in the field of testing and design for testability.
  Deepali Koppad is the research associate working on this project.
• EPSRC EP/C5477861/1: Automatic Test Pattern Generation and Scan Insertion for Asynchronous Circuits
  The overall aim of this project is to develop a methodology for testing asynchronous circuits and implement a tool that will be able to convert a given circuit into a testable equivalent and produce the sequence of test-vectors required for actually performing the test.
  Dilip Vasudevan is the PhD student working on this project.

Teaching

Computer networking INF-CN4/CN5( 4th year, MSc)
2006-07, 05-06, 04-05

Informatics 2C - Computer Systems & Software Engineering
2006-07, 05-06

System Design Project - Group mentor
2004-05 (group won the first prize), 05-06

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