| Journals |
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A. Efthymiou, J. Bainbridge and D. Edwards
"Test Pattern Generation and Partial-Scan Methodology for an Asynchronous
SoC Interconnect"
IEEE Transactions on VLSI systems Accepted for publication. |
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M. Amde, T. Felicijan, A. Efthymiou, D. Edwards and L. Lavagno,
"Asynchronous On-Chip Networks"
IEE Proceedings Computers and Digital Techniques Volume 152, Issue 02, March 2005, p. 273. |
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A. Efthymiou, J.D. Garside,
"A CAM with mixed serial-parallel comparison for use in low energy caches"
IEEE Transactions on VLSI systems, Vol. 12, No. 3, pp. 325-329, March 2004 (special issue on low power design, part 2) |
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S. B. Furber, A. Efthymiou, J.D. Garside, M.J.G. Lewis, D.W. Lloyd and S. Temple,
"Power Management in the AMULET Microprocessors"
IEEE Design and Test of Computers (Ed. E. Macii), Vol. 18 No. 2, pp. 42-52, March-April 2001, pp. 42-52.
[abstract]
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Y. Moisiadis, I. Bouras, A. Efthymiou and C. Papadas,
"A Fast 1-V Bootstrapped Inverter Suitable for Standard CMOS Technologies"
IEE Electronics Letters, Vol. 35, No. 2, pp. 109-111, (1999).
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| Book chapters |
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M. Amde, T. Felicijan, A. Efthymiou, D. Edwards and L. Lavagno,
"Asynchronous On-Chip Networks" (chapter 18)
System On Chip; Next Generation Electronics(provisional title) Bashir Al-Hashimi (Editor), to be published by IEE |
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| Conferences |
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A. Efthymiou, J.D. Garside, I.Papaefstathiou,
"A Low-Power Processor Architecture Optimized for Wireless Devices",
In Proc. of 16th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, July 23-25, 2005.
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A. Efthymiou, J. Bainbridge, and D. Edwards,
"Adding Testability to an Asynchronous Interconnect for GALS SoCs",
In Proc. 2004 IEEE Asian Test Symposium (ATS'04), pp. 20-23, Nov. 2004.
[abstract]
[PDF]
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A. Efthymiou, W. Suntiamorntut, J. Garside and L.E.M. Brackenbury,
"An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm",
In Proc. 10th Intl. Symposium on Asynchronous Circuits and Systems(ASYNC'04), pp. 207-215, Apr. 2004.
[abstract]
[PDF]
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A. Efthymiou, C. Sotiriou and D. Edwards,
"Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits",
In Proc. Design Automation and Test in Europe Conference and Exhibition (DATE'04),
Volume I, p. 672, Feb. 2004.
[abstract]
[PDF]
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A. Efthymiou and J.D. Garside,
"Adaptive Pipeline Structures for Speculation Control",
In Proc. of the 9th Intl. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'03), pp. 46-55, Vancouver, Canada, May 2003.
[abstract]
[PDF]
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A. Efthymiou and J.D. Garside,
"Adaptive Pipeline Depth Control for Processor Power-Management"
In Proc. of the 2002 Intl. Conference on Computer Design (ICCD'02), pp. 454-457, Freiburg, Germany, Sep. 2002.
[abstract]
[PDF]
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A. Efthymiou and J.D. Garside,
"An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks"
In Proc. of the 2002 Intl. Symposium on Low-Power Electronics and Design (ISLPED'02), pp. 136-141, Monterey CA, USA, Aug. 2002.
[abstract]
[PDF]
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A. Efthymiou, J.D. Garside and S. Temple,
"A Comparative Power Analysis of an Asynchronous Processor"
In Proc. of the 11th Intl. Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS'01),
Yverdon-les-bains, Switzerland, Sep. 2001.
[abstract]
[PDF]
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S. B. Furber, A. Efthymiou and M. Singh,
"A Power-Efficient Duplex Communication System"
In Proc. of the 1st Intl. Workshop on Asynchronous Interfaces: tools, techniques and implementations (AINT'2000), pp. 145-150, Delft, The Netherlands, July 2000.
[abstract]
[PDF]
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M. Katevenis, P. Vatsolaki and A. Efthymiou,
"Pipelined Memory Shared Buffer for VLSI Switches"
In Proc. of the ACM SIGCOMM 95 Conference, pp. 39-48,
Cambridge, Massachusetts, USA, August 1995.
[ICS-FORTH: ps.gz]
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M. Katevenis, P. Vatsolaki, A. Efthymiou and M. Stratakis,
"VC-level Flow Control and Centralized buffering in the Telegraphos Switch"
In Proc. of the Hot Interconnects III Symposium, Stanford, USA, August 1995.
[ICS-FORTH: ps.gz]
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| Local workshops |
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A. Efthymiou, J. Bainbridge and D. Edwards,
"Remedy for an asynchronous weakness: a fully-testable interconnect fabric"
4th ACiD-WG Workshop, Turku, Finland, June 2004.
[abstract]
[slides] |
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A. Efthymiou and J.D. Garside,
"Adaptive Pipeline Depth for Asynchronous Systems Using Collapsible Latch Controllers"
13th Asynchronous UK Forum, Cambridge, Dec. 2002.
[PDF] |
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A. Efthymiou,
"Pipeline Occupancy Control for Power Adaptive Processors".
12th Asynchronous UK Forum, London, June 2002.
[PDF] |
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A. Efthymiou,
"The Design of a Low-Power Asynchronous Communication System"
9th Asynchronous UK Forum, Cambridge, Dec. 2000.
[PDF] |
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A. Efthymiou,
"Power Analysis of AMULET3"
Future Directions in Low-Power Design Forum, Manchester, Oct. 2000.
[PDF] |
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| Theses - Technical Reports |
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A. Efthymiou,
"Asynchronous Techniques for Power-Adaptive Processing",
PhD Thesis Dept. of Computer Science, University of Manchester, UK.
[abstract]
[PDF] |
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A. Efthymiou,
"Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-Custom CMOS"
Technical Report FORTH-ICS/TR-143, Institute of Computer Science,
FORTH, Heraklion, Crete, Greece, Master of Science Thesis, Department of
Computer Science, University of Crete. November 1995.
[ICS-FORTH: ps.gz](63 pages).
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M. Katevenis, P. Vatsolaki, A. Efthymiou,
"Pipelined Memory Organization for High Perfomance Switching and Buffering"
Technical Report FORTH-ICS/TR-127, Institute of Computer Science, FORTH, Heraklio,Crete, Greece, December 1994.
[ICS-FORTH: ps.Z](23 pages)
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