Boris Grot
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Conference Publications

Blasting Through The Front-End Bottleneck With Shotgun.
R. Kumar, B. Grot, V. Nagarajan. In 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2018.

Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches.
P. Faldu and B. Grot. In 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2017.

The Mondrian Data Engine.
M. Drumond, A. Daglis, D. Ustiugov, N. Mirzadeh, J. Picorel, B. Falsafi, B. Grot, D. Pnevmatikatos. In 44th International Symposium on Computer Architecture (ISCA), 2017.

Boomerang: a Metadata-Free Architecture for Control Flow Delivery.
R. Kumar, C. Huang, B. Grot, V. Nagarajan. In 23rd International Symposium on High Performance Computer Architecture (HPCA), 2017.

C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches.
C. Huang, R. Kumar, M. Elver, B. Grot, V. Nagarajan. In 49th International Symposium on Microarchitecture (MICRO), 2016.

SABRes: Atomic Object Reads for Rack-Scale In-Memory Computing.
A. Daglis, D. Ustiugov, S. Novakovic, E. Bugnion, B. Falsafi, B. Grot. In 49th International Symposium on Microarchitecture (MICRO), 2016.

The Case for RackOut: Scalable Data Serving Using Rack-Scale Systems.
S. Novakovic, A. Daglis, E. Bugnion, B. Falsafi, B. Grot. In 7th ACM Symposium on Cloud Computing (SOCC), 2016.

Asynchronous Memory Access Chaining.
O. Kocberber, B. Grot, and B. Falsafi. In 42nd International Conference on Very Large Data Bases (VLDB), 2016.

Confluence: Unified Instruction Supply for Scale-Out Servers.
C. Kaynak, B. Grot, and B. Falsafi. In 48th International Symposium on Microarchitecture (MICRO), 2015.

Manycore Network Interfaces for In-Memory Rack-Scale Computing.
A. Daglis, S. Novakovic, E. Bugnion, B. Falsafi, B. Grot. In 42nd International Symposium on Computer Architecture (ISCA), 2015.

BuMP: Bulk Memory Page Access Prediction and Streaming.
S. Volos, J. Picorel, B. Falsafi, B. Grot. In 47th International Symposium on Microarchitecture (MICRO), 2014.

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring.
S. Fytraki, E. Vlachos, O. Kocberber, B. Falsafi, B. Grot. In 20th International Symposium on High Performance Computer Architecture (HPCA), 2014.

Scale-Out NUMA.
S. Novakovic, A. Daglis, E. Bugnion, B. Falsafi, B. Grot. In 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2014.

Meet the Walkers: Accelerating Index Traversals for In-Memory Databases.
O. Kocberber, B. Grot, J. Picorel, B. Falsafi, K. Lim, and P. Ranganathan. In 46th International Symposium on Microarchitecture (MICRO), 2013.
Best Paper Runner-Up.

SHIFT: Shared History Instruction Fetch for Lean-Core Server Processors.
C. Kaynak, B. Grot, and B. Falsafi. In 46th International Symposium on Microarchitecture (MICRO), 2013.

NOC-Out: Microarchitecting a Scale-Out Processor.
P. Lotfi-Kamran, B. Grot, and B. Falsafi. In 45th International Symposium on Microarchitecture (MICRO), 2012.

Scale-Out Processors.
P. Lotfi-Kamran, B. Grot, M. Ferdman, S. Volos, O. Kocberber, J. Picorel, A. Adileh, D. Jevdjic, S. Idgunji, E. Ozer and B. Falsafi. In 39th International Symposium on Computer Architecture (ISCA), 2012.

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.
S. Volos, C. Seiculescu, B. Grot, N. Khosro Pour, B. Falsafi and G. De Micheli. In 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2012.

Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees.
B. Grot, J. Hestness, S. W. Keckler and O. Mutlu. In 38th International Symposium on Computer Architecture (ISCA), 2011. IEEE Micro Top Pick in Computer Architecture.

Reducing Network-on-Chip Energy Consumption through Spatial Locality Speculation.
H. Kim, P. Ghoshal, B. Grot, P. Gratz and D. Jimenez. In 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 2011.

Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-a-Chip.
B. Grot, S. W. Keckler and O. Mutlu. In 42nd International Symposium on Microarchitecture (MICRO), 2009.

Express Cube Topologies for On-Chip Interconnects.
B. Grot, J. Hestness, S. W. Keckler and O. Mutlu. In 15th International Symposium on High Performance Computer Architecture (HPCA), 2009.

Regional Congestion Awareness for Load Balance in Networks-on-Chip.
P. Gratz, B. Grot and S. W. Keckler. In 14th International Symposium on High Performance Computer Architecture (HPCA), 2008.


Journal Publications

Fat Caches for Scale-Out Servers.
S. Volos, D. Jevdjic, B. Falsafi, B. Grot. IEEE Micro. Volume XX, issue YY. 2016.
Technical Report.

Optimizing Datacenter TCO with Scale-Out Processors.
B. Grot, D. Hardy, P. Lotfi-Kamran, C. Nicopoulos, Y. Sazeides, B. Falsafi. IEEE Micro, Special Issue on Energy-Aware Computing. Volume 32, issue 5. Sep/Oct 2012.

A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips.
B. Grot, J. Hestness, S. W. Keckler and O. Mutlu. IEEE Micro, Top Picks 2012 -- Special Issue. Volume 32, issue 3. May/June 2012. (original in ISCA 2011)

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.
H. Kim, B. Grot, P. V. Gratz, D. A. Jimenez. IEEE Transactions on Computers, Special Section on NOCS. To appear.


Peer-Reviewed Workshop Publications

Reuse-Aware Management for Last-Level Caches.
P. Faldu and B. Grot. In 2nd Cache Replacement Competition, 2017.

LLC Dead Block Prediction Considered Not Useful.
P. Faldu and B. Grot. In 13th Workshop on Duplicating, Deconstructing and Debunking (WDDD), 2016.

Sort vs. Hash Join Revisited for Near-Memory Execution.
N. Mirzadeh, O. Kocberber, B. Falsafi, B. Grot. In Fifth Workshop on Architectures and Systems for Big Data (ASBD), 2015.

Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation.
J. Hestness, B. Grot, S. W. Keckler. 3rd International Workshop on Network on Chip Architectures (NoCArc), 2010.

Topology-aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors.
B. Grot, S. W. Keckler and O. Mutlu. 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), 2010.

Segment Gating for Static Energy Reduction in Networks-On-Chip.
K. C. Hale, B. Grot and S. W. Keckler. 2nd International Workshop on Network on Chip Architectures (NoCArc), 2009.

Ocin_tsim: a DVFS-aware simulator for NoC based platforms.
S. Prabhu, B. Grot, P. V. Gratz and J. Hu. 1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), 2009.

Scalable On-chip Interconnect Topologies.
B. Grot and S. W. Keckler. 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), 2008.

Good Memories: Enhancing Memory Performance for Precise Flow Tracking.
B. Grot and W. Mangione-Smith. Advanced Networking and Communications Hardware Workshop (ANCHOR), 2005.


Other

Network-on-Chip Architectures for Scalability and Service Guarantees.
Boris Grot. Ph.D. Thesis, The University of Texas at Austin, August 2011.