[1] P.-J. Micolet, A. Smith, and C. Dubach. A machine learning approach to mapping streaming workloads to dynamic multicore processors. In Proceedings of the 17th ACM SIGPLAN/SIGBED conference on Languages, Compilers and Tools for Embedded Systems, LCTES, 2016. [ bib ]
[2] T. Remmelg, T. Lutz, M. Steuwer, and C. Dubach. Performance portable gpu code generation for matrix multiplication. In Proceedings of the 2016 Workshop on General Purpose Processing on Graphics Processing Units, GPGPU, 2016. [ bib ]
[3] E. Tomusk, C. Dubach, and M. O'Boyle. Four metrics to evaluate heterogeneous multicores. In International Conference on High Performance Embedded Architectures & Compilers, HiPEAC, 2016. [ bib ]
[4] A. Harries, M. Steuwer, M. Cole, A. Gray, and C. Dubach. Compositional compilation for sparse, irregular data parallelism. In Proceedings of the 2016 Workshop on High-Level Programming for Heterogeneous and Hierarchical Parallel Systems, HLPGPU, 2016. [ bib ]
[5] E. Tomusk, C. Dubach, and M. O'Boyle. Four metrics to evaluate heterogeneous multicores. ACM Transactions on Architecture and Code Optimization, ACM TACO, 12(4), 2015. [ bib ]
[6] E. Tomusk, C. Dubach, and M. O'Boyle. Diversity: A design goal for heterogeneous processors. IEEE Computer Architecture Letters, IEEE CAL, PP, 2015. [ bib ]
[7] M. Miller, D. Holden, R. Al-Ashqar, C. Dubach, K. Mitchell, and T. Komura. Carpet unrolling descriptors for character control on uneven terrain. In Proccedings of the ACM SIGRAPH Motion in Games Conference, MIG, 2015. [ bib ]
[8] M. Steuwer, C. Fensch, S. Lindley, and C. Dubach. Generating performance portable code using rewrite rules: From high-level functional expressions to high-performance opencl code. In Proceedings of the 20th ACM SIGPLAN International Conference on Funcational Programming, ICFP, 2015. [ bib ]
[9] J. J. Fumero, T. Remmelg, M. Steuwer, and C. Dubach. Runtime code generation and data management for heterogeneous computing in java. In Proccedings of the 12th International Conference on Principles and Practice of Programming on the Java Platform: Virtual machines, languages, and tools, PPPJ, 2015. [ bib ]
[10] M. Steuwer, C. Fensch, and C. Dubach. Patterns and rewrite rules for systematic code generation (from high-level functional patterns to high-performance opencl code). arXiv Technical Report arXiv:1502.02389, 2015. [ bib | .pdf ]
[11] A. Magni, C. Dubach, and M. O'Boyle. Automatic optimization of thread-coarsening for graphics processors. In Proceedings of the 23rd international conference on Parallel architectures and compilation, PACT, 2014. [ bib | .pdf ]
[12] E. Tomusk, C. Dubach, and M. O'Boyle. Measuring flexibility in single-isa heterogeneous processors. In Proceedings of the 23rd international conference on Parallel architectures and compilation, PACT, 2014. [ bib | .pdf ]
[13] J. J. Fumero, M. Steuwer, and C. Dubach. A composable array function interface for heterogeneous computing in java. In Proceedings of ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming, ARRAY, 2014. [ bib | .pdf ]
[14] G. Fursin and C. Dubach. Community-driven reviewing and validation of publications. In Proceedings of the 1st ACM SIGPLAN Workshop on Reproducible Research Methodologies and New Publication Models in Computer Engineering, TRUST, 2014. [ bib | .pdf ]
[15] A. Magni, C. Dubach, and M. O'Boyle. Exploiting gpu hardware saturation for fast compiler optimization. In Proceedings of Workshop on General Purpose Processing Using GPUs, GPGPU, 2014. [ bib | .pdf ]
[16] A. Magni, C. Dubach, and M. F. P. O'Boyle. A large-scale cross-architecture evaluation of thread-coarsening. In Proceedings of the 2013 Conference on High Performance Computing Networking, Storage and Analysis, SC, 2013. [ bib | .pdf ]
[17] C. Dubach, T. M. Jones, and E. V. Bonilla. Dynamic microarchitectural adaptation using machine learning. ACM Transactions on Architecture and Code Optimization, ACM TACO, 10(4):31, 2013. [ bib | .pdf ]
[18] C. Dubach, P. Cheng, R. Rabbah, D. Bacon, and S. Fink. Compiling a high-level language for gpus (via language support for architectures and compilers). In Proceedings of the 33rd ACM SIGPLAN Symposium on Programming Language Design and Implementation, PLDI, 2012. [ bib | .pdf ]
[19] C. Dubach, T. M. Jones, and M. F. O'boyle. Exploring and predicting the effects of microarchitectural parameters and compiler optimizations on performance and energy. ACM Transactions on Embedded Computing Systems, ACM TECS, 11(1):24, 2012. [ bib | .pdf ]
[20] C. Dubach, T. M. Jones, and M. F. O'Boyle. An empirical architecture-centric approach to microarchitectural design space exploration. IEEE Transactions on Computers, IEEE TC, 60(10):1445--1458, 2011. [ bib | .pdf ]
[21] C. Dubach, T. M. Jones, E. V. Bonilla, and M. F. P. O'Boyle. A predictive model for dynamic microarchitectural adaptivity control. In Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO, 2010. [ bib | .pdf ]
[22] C. Dubach, T. M. Jones, E. V. Bonilla, G. Fursin, and M. F. P. O'Boyle. Portable compiler optimisation across embedded programs and microarchitectures using machine learning. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO, 2009. [ bib | .pdf ]
[23] C. Dubach, T. M. Jones, and M. F. O'Boyle. Rapid early-stage microarchitecture design using predictive models. In Proceedings of the 2009 IEEE International Conference on Computer Design, ICCD, 2009. [ bib | .pdf ]
[24] C. Dubach. Using machine-learning to efficiently explore the architecture/compiler co-design space. PhD Thesis, 2009. [ bib | .pdf ]
[25] C. Dubach, T. M. Jones, and M. F. O'Boyle. Exploring and predicting the architecture/optimising compiler co-design space. In Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES, 2008. [ bib | .pdf ]
[26] C. Dubach, J. Cavazos, B. Franke, G. Fursin, M. F. O'Boyle, and O. Temam. Fast compiler optimisation evaluation using code-feature based performance prediction. In Proceedings of the 4th International Conference on Computing Frontiers, CF, 2007. [ bib | .pdf ]
[27] C. Dubach, T. M. Jones, and M. F. P. O'Boyle. Microarchitectural design space exploration using an architecture-centric approach. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO, 2007. [ bib | .pdf ]
[28] J. Cavazos, C. Dubach, F. Agakov, E. Bonilla, M. F. P. O'Boyle, G. Fursin, and O. Temam. Automatic performance model construction for the fast software exploration of new hardware designs. In Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES, 2006. [ bib | .pdf ]
[29] M. Vuletic, C. Dubach, L. Pozzi, and P. Ienne. Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS, 2005. [ bib | .pdf ]
[30] C. Dubach. Java byte code synthesis for reconfigurable computing platforms. Master's thesis, 2005. [ bib | .pdf ]