Contact

Address:
The University of Edinburgh
IF 1.25
Informatics Forum
10 Crichton Street
Edinburgh, EH8 9AB

E-mail:

cheng-chieh.huang [at] ed.ac.uk

I amwas a postdoc in the School of Informatics at the University of Edinburgh, under the supervision of Vijay Nagarajan and Boris Grot. I am a member of the Institute for Computing Systems Architecture.
My research interest focuses on computer architecture with special emphasis on
  • Memory systems and near-data processing in large-scale datacenters.
  • Processor architecture and microarchitecture.
  • Architectural support for approximate computing.
  • Operating system support for emerging memory technologies.
  • Teaching Assistant: Computer Architecture (University of Edinburgh), 2016.
  • Teaching Assistant: Parallel Architecture (University of Edinburgh), 2014.
  • R. Kumar, C. Huang, B. Grot and V. Nagarajan, Boomerang: a Metadata-Free Architecture for Control Flow Delivery, The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA), Austin, USA, February 2017.
  • C. Huang, V. Nagarajan and A. Joshi, DCA: a DRAM-Cache-Aware DRAM Controller, The IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Salt Lake City, Utah, USA, November 2016.
  • C. Huang, R. Kumar, M. Elver, B. Grot and V. Nagarajan, C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches, The 49th ACM/IEEE International Symposium on Microarchitecture (MICRO), Taipei, Taiwan, October 2016.
  • C. Huang and V. Nagarajan, Increasing Cache Capacity via Critical-words-Only Cache, The 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, October 2014.
  • C. Huang and V. Nagarajan, ATCache: Reducing DRAM Cache Latency via a Small SRAM Tag Cache, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Edmonton, Canada, August 2014.