Kees Goossens, Professor

Position

As of January 2010, full-time full professor in Real-Time Embedded Systems
in the Electronic Systems group
in the Electrical Engineering faculty
at the Eindhoven University of Technology (TU/e).

The Eindhoven University of Technology is ranked high in university rankings. It is the best Netherlands university, according to the Times Higher Education Supplement and the fiftieth best university in the world, according to the THES ranking.

I regularly visit the Computer Engineering group at the Delft University of Technology for supervision of promovendi and collaboration.

News

We often have open PhD positions in the Electronic Systems group on topics such as real-time (predictability), performance virtualisation (a.k.a. temporal isolation, composability), networks on chip, SDRAM memory controllers, energy & power minimisation/minimization, dataflow formalisms (SDF3) for performance evaluation, etc. Inquire directly (see email on contact page).
At ESWEEK in October 2011 in Taiwan
- Saddek Bensalem and I organised the Time-Predictable and Composable Architectures for Dependable Embedded Systems tutorial, with speakers
  Slides are now online below
  1. Prof. Sifakis - Rigorous Component-based System Design in BIP
  2. Prof. Obermaisser - Time-Triggered Architecture -- Concepts, Applications and Research Challenges
  3. Prof. Goossens - Composable Timing and Energy in CompSOC
  4. Prof. Lee - Repeatable Timing in Software and Networks
  5. Prof. Kirsch - The Logical Execution Time Paradigm
  The tutorial abstract that is in the proceedings:
  "Time-predictable and composable architectures for dependable embedded systems"
- Benny Akesson and I organised the Memory controllers for High-performance and real-time MPSoCs special session, with speakers
  Slides are now online below
  1. Drew Wingard, Sonics Inc., USA: High performance memory subsystems for consumer multi-core SoCs
  2. Tei-Wei Kuo, National university of Taiwan, Taiwan: Challenges and solutions for consumer flash-memory devices
  3. Denis Dutoit, CEA LETI, France: 3D Technologies: Some Perspectives for Memory Interconnect and Controller
  4. Benny Akesson, Kees Goossens, Eindhoven University of Technology, the Netherlands: SDRAM controllers for Mixed Time-Criticality Systems
  The special session paper that is in the proceedings is:
  "Memory controllers for high-performance and real-time MPSoCs --- Requirements, architectures, and future trends"
'Memory Controllers for Real-Time Embedded Systems' by Benny Akesson will be published in September 2011 by Springer in their Embedded Systems Series.
Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.
This book is generally intended for readers interested in Systems-on-Chips with real-time applications. It is especially well-suited for readers looking to use SDRAM memories in systems with hard or firm real-time requirements. There is a strong focus on real-time concepts, such as predictability and composability, as well as a brief discussion about memory controller architectures for high-performance computing.
For more information see here.
We received the HiPEAC paper award for our paper
"The Aethereal Network on Chip after Ten Years: Goals, Evolution, Lessons, and Future"
which was presented at the DAC 2010 Special Session on Ten Years of Networks on Chip.
presentation
'On-Chip Interconnect with aelite', i.e. 'Aethereal, the book' by Andreas Hansson was published in November 2010 by Springer in their Embedded Systems Series.
It contains a general but thorough introduction to predictability (real-time performance) and composability (performance virtualization), why we need them, what they are, and how they are implemented. Then the Aethereal network on chip concepts, hardware architecture, software/driver architecture, and design flow are described in full detail. An examples chapter ties all together. Finally, a case study (previously unpublished) applies the proposed concepts to two industrial SOCs.
For more information see here.

Research Topics

all aspects of networks on chip
- especially the Aethereal Network on Chip (NOC) developed since 2001 by Philips/NXP Research
- network on chip design flows
- hardwired networks on chip in FPGAs
- network on chip as test access mechanism (TAM)
- uses of networks on chip, e.g. for internet router crossbars
- communication protocols
embedded multi-processor systems
- composability (cf. virtualisation), especially of temporal behaviour
- predictability, for real-time applications
- abstraction, especially transaction-based communication-centric debug
memory controllers
reducing complexity
new challenges
- low power for real time applications
- variability in all its aspects
- 3D integration

See the Research and Publication pages for more details.

Much of this research has been performed as part of national and international research projects, including MESA, NEVA, TSAR, COMCAS, SCALOPES, 3DIM3, INDEXYS, NEST, Flextiles, T-CREST.

All the research is in collaboration with MSc and PhD students, postdocs, and other researchers at NXP Semiconductors, Delft university of technology, and other (Dutch) universities.

Other Positions

TODAES 2009-present Editorial board member for the Association for Computing Machinery (ACM) Transactions on Design Automation of Electronic Systems.
DAEM 2006-present Associate editor for the Springer Journal of Design Automation of Embedded Systems.
IJECRTS 20011-2013 Editorial Review Board member of the Resources Management Association (IRMA) International Journal of Embedded and Real-Time Communication Systems.
CDT 2008 Guest editor for the IET Computers and Digital Techniques special issue on networks on chip.
DAEM 2011 Guest editor for the Springer Journal of Design Automation of Embedded Systems for the special issue on on Networks on chips: design flows and case studies.

Previous Positions

Senior Principal Research Scientist at NXP Semiconductors (formerly Philips) Research (September 1995 to December 2009).
Part-time Adjunct (Full) Professor (Buitengewoon Hoogleraar) at Computer Engineering group at the Delft University of Technology (February 2007 to December 2009).
Post-doctoral positions at the Departamento de Informatica, Universidade Federal de Pernambuco, Brazil, and Dipartimento di Scienze dell'Informazione, Universita di Roma "La Sapienza", Italy (1993-1995).
My PhD in Computer Science is from the Laboratory for Foundations of Computer Science, of the University of Edinburgh, UK (1998-1993). My thesis treated Embedding Hardware Description Languages in Proof Systems, which involved operational semantics for a subset of the ELLA hardware description language, and embedded this semantics in the higher-order-logic proof system Lambda, and proving various properties about the embedded semantics, formal hardware synthesis, and symbolic simulation.
My BSc in Computer Science and Pure Mathematics is from the Computer Science department of the University of Wales, UK (1984-1988).

Previous Research Topics

automated theorem proving for hardware verification. In particular, my PhD thesis describes the embedding of the formal semantics of a hardware description language (ELLA, VHDL, etc.) in the Lambda higher-order logic theorem prover.
high-level hardware synthesis design flow for high-throughput video processing, in particular the Philips Phideo architecture and design flow.
on-chip communication protocols for global (interchannel) resource management, and dynamic reconfiguration.

More information

In increasing information content, but surely out of date:

A respectable passport photograph for work purposes
50 word research biography
120 word research biography
CV