Cellular Multiprocessors

Supported by:

(#GR/S79572/01)

(#IP 27648 (FP6))

(#443570)

Principal Investigator

Marcelo Cintra - School of Informatics - University of Edinburgh

Research Assistants

Christian Fensch (Ph.D. 2008) - School of Informatics - University of Edinburgh
Pedro Díaz (Ph.D. candidate) - School of Informatics - University of Edinburgh
Vasileios Porpodas (Ph.D. candidate) - School of Informatics - University of Edinburgh

Tom Ashby (Post-doc - 2005-2007) - School of Informatics - University of Edinburgh

Research Collaborators

Michael O'Boyle - School of Informatics - University of Edinburgh
Wolfgang Karl - Faculty of Informatics - University of Karlsruhe
Manuel E. Acacio - Department of Computer Engineering and Technology - University of Murcia

Project Objectives

To investigate the use of single chip multiprocessor architectures based on the replication of very simple processor-memory "cells". This investigation follows two main lines of research. The first is the development of novel compilation techniques to extract larger degrees of TLP from traditionally hard to parallelise applications. The second is the development of improved architectures through the systematic study of architectural design alternatives under various performance, complexity, and power dissipation constraints.

Project Contributions

In [4] we proposed a hybrid software-hardware mechanism for cache coherence in tiled CMPs with scalable on-chip interconnects. The mechanism is relies on hardware to perform remote cache accesses and moves the responsibility for data mapping and coherence to the OS.

In [3] we presented a tool that can be used to identify the breakdown of cache miss types and, thus, assist programmers in improving the data locality behavior of their programs.

In [2] we proposed a novel class of hardware prefetchers that allow the global miss address stream to be first localized according to different correlation criteria and later chained following their original temporal behavior. This mechanism allows for the simultaneous exploitation of different types of correlation while maintaining timeliness.

Publications (sorted by date)

[1] Distance-Aware Round-Robin Mapping for Large NUCA Caches
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, and Jose M. Garcia
Intl. Conf. on High Performance Computing (HiPC), December 2009

[2] Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
Pedro Diaz and Marcelo Cintra
Intl. Symp. on Computer Architecture (ISCA), p 81-92, June 2009

[3] A Generic Tool Supporting Cache Design and Optimisation on Shared Memory Systems
Martin Schindewolf, Jie Tao, Wolfgang Karl, and Marcelo Cintra
Wksp. on Parallel Systems and Algorithms (PASA), February 2008

[4] An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Christian Fensch and Marcelo Cintra
Intl. Symp. on High-Performance Computer Architecture (HPCA), p 355-366, February 2008

Thesis

An OS-Based Alternative to Full Hardware Coherence on Tiled Chip-Multiprocessors.
Christian Fensch
Ph.D., School of Informatics, University of Edinburgh, 2008.

Talks

Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
Department of Informatics, University of Munich, Munich, Germany, November 2009

Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching (presentation)
Intl. Symp. on Computer Architecture, Austin, USA, June 2009

Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, USA, May 2009

An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Department of Electrical and Computer Engineering, University of Rochester, Rochester, USA, March 2009

An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Intel Germany Research Laboratory, Braunschweig, Germany, July 2008

An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Department of Computer Engineering, Universidad de Murcia, Murcia, Spain, May 2008

An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs (presentation)
Intl. Symp. on High-Performance Computer Architecture, Salt Lake City, USA, February 2008

Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs (presentation)
IBM T. J. Watson Research Center, Yorktown Heights, USA, July 2007

Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs
Department of Informatics, University of Erlangen-Nuremberg, Erlangen, Germany, June 2007

Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs
Oak Ridge National Laboratory, Oak Ridge, USA, March 2007

Alternatives to Eager Hardware Cache Coherence on Large-Scale CMPs
ARM Ltd., Cambridge, UK, February 2007