I am a Research Associate in the Compiler and Architecture (CArD) group working with Vijay Nagarajan and Boris Grot. I received my PhD from Department of Computer Architecture, Universitat Politècnica de Catalunya (UPC), Barcelona in July 2014. My dissertation research was focused on optimizing SIMD execution in HW/SW co-designed processors and was carried out in ARCO research group led by Prof. Antonio González. I worked as a Graduate Intern Researcher in Intel Barcelona Research Center, Intel Labs from Oct 2013 to May 2014. During my stint at Intel Labs, I worked on memory controllers for emerging memory technologies.
Doctor of Philosophy, Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain. July 2014.
Thesis : Optimizing SIMD Execution in HW/SW Co-designed Processors.
Advisors : Dr. Alejandro Martínez and Prof. Antonio González.
Master of Engineering, Microelectronics, Birla Institute of Technology and Science (BITS) Pilani , India. Dec 2008.
Thesis : Cache Design issues for Multi-core Architectures.
Advisor : Prof. TSB Sudarshan.
Bachelor of Technology, Electronics and Communications Engineering, Kurukshetra University, India. July 2005.
Marks : 75.4%.
Program Committee: ICPP(2017)
Reviewer (Not PC/ERC): HPCA(2017, 2016, 2013), SC(2016), CGO(2016), ASPLOS(2015), ISCA(2015), NAS(2015)
Journal Review: IEEE Transactions on Computers
Co-developer of DARCO, an infrastructure for research on HW/SW co-designed Virtual Machines.