About

I am a Research Associate in the Compiler and Architecture (CArD) group working with Vijay Nagarajan and Boris Grot. I received my PhD from Department of Computer Architecture, Universitat Politècnica de Catalunya (UPC), Barcelona in July 2014. My dissertation research was focused on optimizing SIMD execution in HW/SW co-designed processors and was carried out in ARCO research group led by Prof. Antonio González. I worked as a Graduate Intern Researcher in Intel Barcelona Research Center, Intel Labs from Oct 2013 to May 2014. During my stint at Intel Labs, I worked on memory controllers for emerging memory technologies.

Work Experience

  • Intel Barcelona Research Center, Intel Labs. Graduate Intern Researcher. (Oct 2013 - May 2014).
    • Worked on memory controllers for emerging memory technologies.
    • Received Intel Spontaneous Level II/Excellence Award.

  • Birla Institute of Technology and Science (BITS), Pilani, India. Assistant Lecturer. (Jan 2009 - July 2009).
    • Co-taught a course on Microprocessor Programming and Interfacing to a class of more than 250 students.

  • Birla Institute of Technology and Science (BITS), Pilani, India. Teaching Assistant. (Sept 2006 - July 2008).
    • Preparing, conducting and evaluating tutorials and lab sessions for undergraduate courses including Digital Electronics and Microprocessors, Microelectronic Circuits, Electronic Devices and Integrated Circuits, etc.

  • Himachal Futuristic Communication Ltd, India. Graduate Engineer Trainee. (July 2005 - July 2006).
    • Video headend and optical fiber network installation/operation as a part of Internet Protocol TV project.
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Education

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Professional Services

  • Program Committee: ICPP(2017)

  • Reviewer (Not PC/ERC): HPCA(2017, 2016, 2013), SC(2016), CGO(2016), ASPLOS(2015), ISCA(2015), NAS(2015)

  • Journal Review: IEEE Transactions on Computers

  • Co-developer of DARCO, an infrastructure for research on HW/SW co-designed Virtual Machines.