Instruction issue

All instructions in the CRAY-1 are accessed from within the instruction buffers; if an instruction request cannot be satisfied by any of the four buffers, a 64-parcel block of instructions is transferred from memory into one of them. A new instruction is accessed whenever the P register (program counter) is updated. For sequential instructions this occurs as an instruction parcel enters the Next Instruction Parcel register (NIP in the figure). From NIP the instruction parcel is copied into the Current Instruction Parcel register (CIP), where it waits to be issued. In the case of a 32-bit instruction the second parcel is contained in the Lower Instruction Parcel register (LIP) which is loaded in parallel with NIP.

As in the case of the CDC 7600, an instruction is only issued when the conditions in the functional units and operating registers are such that the instruction can be carried through to completion without conflicting with any previously issued, but as yet uncompleted instructions. Thus although any number of the V registers can, in principle, accept results in a single clock period, the A and S registers are similar to the X registers in the 7600; only one A register and one S register can accept a result in any one clock period. Issue of an instruction is therefore delayed if it would cause a result to arrive at either of these sets of registers at the same time as a result from a previously issued instruction.

The CRAY-1 also uses a reservation mechanism similar to that in the CDC 7600. When an instruction is issued which will deliver a new result to an A, S or V register, a reservation is set for that register which prevents the issuing of any subsequent instruction requiring the use of that register until the result has been delivered. In the case of a V register the reservation is for the whole register, rather than individual elements, and furthermore, during the execution of a vector operation, reservations are placed on the operand V registers as well as on the result register. These reservations do not apply to an S register taking part in a vector operation, however, or to the VL register, since their values are copied into the unit carrying out the operation as the instruction is issued. The registers themselves are then immediately free to participate in subsequent instructions.

The need to reserve the operand V registers arises from the nature of the integrated circuits used in the construction of the V registers. These each contain 16 x 4 bits, representing 4 data bits in each of 16 vector register elements, and only one set of 4 bits can be accessed in any one clock period. If two vector instructions using the same operand V registers were in progress at the same time, they would require access to two different elements simultaneously. The same argument applies to the result register; it is impossible to read one element from within a vector register while a new value is being written into another element. The only exception to this rule occurs when an element value which is being delivered to a vector register can, in the same clock period, be routed back into another functional unit as an input operand. This arrangement allows chaining of vector operations, and thus allows much more effective use to be made of the parallel functional units than was possible in the CDC 6600 or 7600.