MU5

MU5 was the 5th Manchester University computer following the Mark I, Mercury, the MV 950 and Atlas. The project began in 1966 with the aim of building a machine 20x as fast as Atlas for users. It was led by Tom Kilburn with Derrick Morris leading the software team and Dai Edwards leading the hardware team, with David Aspinall as his deputy. The SERC funded the project with a £630k grant over 5 years and ICL agreed to manufacture the hardware for the machine at cost price.

The MU5 console (centre foreground) with the machine in the background. Left to right: Pat McKissack (secretary to Prof Edwards), Simon Lavington, Gordon Frank, Roland Ibbett, Peter Whitehead, Tony Whitehouse, Lynne Plant (seated at the System Performance Monitor).

The main design aim for MU5 was fast, efficient processing of high-level language programs in an interactive environment. This required an instruction set that would allow: generation of efficient code by compilers to be easy; programs to be compact; the processor to be pipelined for fast operation; information on the nature of operands to be available to the hardware to allow optimal operand buffering. Algol and FORTRAN were typical of two major classes of programming languages in common use at the time, both using routines and having the following features:

  1. Each routine had local working space containing named variables of integer (fixed-point) and real (floating-point) types, and named structured data sets e.g. arrays.
  2. A routine could also refer to non-local names, either in an enclosing routine or in a workspace common to all routines.
  3. Statements could involve an arbitrary number of operands of any of the named types, function calls or constants.
Reconciling these features with the requirements for the instruction set meant having an address form corresponding to each of the different operand forms and specifying only one operand in each instruction. Also, there would be no addressable fast registers, firstly to eliminate the need for compilers to optimise their use, secondly to avoid the need to dump and restore their values during routine entry and exit and process changes. Instead, MU5 had a small associatively addressed Name Store containing 32 64-bit words that formed a part of the one-level store of the machine. Addresses were segmented virtual addresses, with named variables being held in Segment 0.

The Name Store was part of the Primary Operand Unit which decoded each instruction and fetched its primary operand: a 32-bit value, a 64-bit value, a 64-bit descriptor or a literal value. If the operand was a descriptor, the instruction was sent to the Secondary Operand Unit where the descriptor was interpreted and the secondary operand accessed. Descriptors contained an Origin field, a Bound field, an operand Size field and a Type field, the most commonly used type accessing an array element by adding a Modifier, sent from the single B-register, to the Origin and checking the Modifier against the Bound field. Similarly to the Name Store, an Operand Buffer System in the Secondary Operand Unit included, in this case, 8 128-bit words containing array elements. The Descriptor Operand Processing Unit selected the specified size of element from the within one of these words.

The Instruction Buffer Unit prefetched instructions from the Local Store but, because jump instructions could disrupt the flow of sequential instructions, included a jump history table, the Jump Trace, that attempted to predict the result of an impending jump instruction, based on its address, and so prefetch the instructions required for a loop.

MU5 Processor Architecture

The MU5 processor formed part of a complex of computers and backing stores, with an ICL 1905E handling conventional peripherals and a PDP 11/10 processor handling terminals and acting as a disk file controller. Transfers between these devices were implemented in hardware by an 'Exchange', which allowed single 64-bit parallel word transfers between units at a rate of one every 100 ns.

MU5 was built by ICL using Mototrola’s MECL 2.5 small-scale Emitter Coupled Logic integrated circuits mounted on small integrated circuit boards known as modules. The modules were plugged into 13” x 16” 'platters', each with a capacity of 200 modules. ECL enabled a 50ns minimum instruction execution time (like Atlas, MU5 was asynchronous) compared to the 2µs of Atlas.

The MU5 Complex

A new operating system, MUSS, was created for MU5. MUSS was designed to be adaptable to a range of processors and in the MU5 complex all three machines ran MUSS. MUSS was a small kernel that implemented an arbitrary set of virtual machines. The MUSS code appeared in segments that were common to each virtual machine's virtual address space. Once it was fully commissioned, in October 1974, MU5 ran a valuable computing service for up to 25 active on-line users (out of a user community of about 100) in the Department until it was dismantled in 1982.

To find out more about MU5, go to IEEE Engineering and Technology History Wiki: MU5