Recent Updates

Started working for Intel Labs, Barcelona 

All settled up and started working.

Paper accepted in HPCA 

Our paper got accepted in HPCA 2010!! Check the publications section.

Found a Job 

I will soon be joining Intel Labs, Barcelona to work as a research scientist.

Defended my thesis 

I have now defended my thesis and I am officially done with my PhD degree!

Welcome to my Homepage!

I just joined Intel Labs, Barcelona. I am currently a research scientist working on computer architecture.

I finished my PhD at the University of Edinburgh on August 2009. During my last year in Edinburgh (2008-2009), I was also a research assistant for the iTLS project, which is a joint work between the University of Edinburgh and the University of Manchester.

My adviser was Marcelo Cintra,  and I was part of the  Compiler and Architecture Design group (CArD). For my PhD thesis my main focus was on how to  combine different speculative multithreaded execution models.

Before joining the University of Edinburgh, I obtained my Diploma in Electrical and Computer Egineering from the University of Patras, Greece. My adviser there was Stefanos Kaxiras.

Research:

My main research area is computer architecture, with an emphasis on performance and low power design. 
My current research areas include:

• Speculative Multithreaded Execution Models
• Thread Level Speculation / Transactional Memory
• Machine Learning Design Space Exploaration
• Low Power Cache Design
• Thermal Aware Leakage Power Reduction

Publications:

• Handling Branches in TLS Systems with Multi-Path Execution.
  Intl. Conf. on High Performance Computer Architecture (HPCA), January 2010.
  
  
• Mixed Speculative Multithreaded Execution Models.
  PhD Thesis, School of Informatics, University of Edinburgh, July 2009.
  
  
• Combining Thread Level Speculation, Helper Threads and Runahead Execution.
  Intl. Conf. on Supercomputing (ICS), June 2009.
  
  
• Using Predictive Modeling for Cross-Program Design Space Exploration in Multicore Systems.
  Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), September 2007.
  
  
• Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.
  Trans. on High Performance and Embedded Architectures and Compilers (HiPEAC Journal), 2(1):2-20, 2007.
  
  
• Applying Decay to Reduce Dynamic Power in Set-Associative Caches.
  Intl. Conf. on High Performance and Embedded Architectures and Compilers (HiPEAC), January 2007.
  
  
• A Simple Mechanism to Adapt Leakage-Control Policies to Temperature.
  Intl. Symp. on Low Power Electronics and Devices (ISLPED), August 2005.
  
  
• 4T-Decay Sensors: A New Class of Small, Fast, Robust, and Low-Power, Temperature/Leakage Sensors.
  Intl. Symp. on Low Power Electronics and Devices (ISLPED), August 2004.
  
  

Talks:

• Combining Thread Level Speculation, Helper Threads and Runahead Execution.
  Intl. Conf. on Supercomputing, 2009.
  
  
• Combining Thread Level Speculation, Helper Threads and Runahead Execution.
  University of Murcia, Department of Computer Science, 2009.
  
  
• Designing CMPs: So Many Options So Little Time.
  Informatics Jamboree, University of Edinburgh, 2008.
  
  
• Microarchitectural Design for TLS Systems.
  National Technical University of Athens, Electrical and Computer Engineering Department, 2008.
  
  
• Applying Decay to Reduce Dynamic Power in Set-Associative Caches.
  Intl. Conf. on High Performance and Embedded Architectures and Compilers, 2007.
  
  
• A Simple Mechanism to Adapt Leakage-Control Policies to Temperature.
  Intl. Symp. on Low Power Electronics and Devices, 2005.
  
  

 

Curriculum Vitae
 CV (in pdf format)

Contact Details

 Email:
 p.xekalakis (at) ed  (dot) ac (dot) uk

 Phone:
 +34938001050

 Address:
 c/ Jordi Girona 1-3
Modul C6
08034 Barcelona, Spain