Vasileios Porpodas Homepage
1.05 Informatics Forum
10 Crichton Street
Edinburgh, EH8 9AB
Tel: 0044 131 650 5146
I am a 4th year PhD student in the Institute for Computing Systems Architecture
, School of Informatics
, University of Edinburgh
under the supervision of prof. Marcelo Cintra
I am a member of the CArD - Compiler and Architecture Design Group
A large part of my research was part of the ERA
My scholarship is provided by EPSRC
My research is on back-end compiler optimizations for scalable computer architectures. In more detail I am interested in:
- Code generation
- Instruction scheduling algorithms for statically scheduled architectures
- Compiler-based error detection
- Scalable clustered architectures and micro-architecture
- Automatic Vectorization and Code generation for architectures with SIMD units
All of my current compiler-related work is implemented in GCC
LUCAS: Latency-adaptive Unified Cluster Assignment and instruction Scheduling. Vasileios Porpodas and Marcelo Cintra.
Conf. on Languages, Compilers and Tools for Embedded Systems (LCTES), June 2013.
[IPDPS] CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores. Konstantina Mitropoulou, Vasileios Porpodas and Marcelo Cintra.
Intl. Parallel & Distributd Processing Symposium (IPDPS), March 2013.
[LCPC] UCIFF: Unified Cluster Assignment, Instruction Scheduling, and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores.
Vasileios Porpodas and Marcelo Cintra.
Intl. Wksp. on Languages and Compilers for Parallel Computing (LCPC), September 2012.
[HPCA] Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs.
Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham and Björn Franke.
Intl. Symp. on High-Performance Computer Architecture (HPCA), February 2012.
Publications up to 2009
[JSPS] Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy. A. Milidonis, N. Alachiotis, V. Porpodas, H. Michail, G. Panagiotakopoulos, A.P. Kakarountas, and C.E. Goutis.
Journal of Signal Processing Systems (JSPS), pages 1-16, 2009.
[CDT] Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse. A. Milidonis, V. Porpodas, N. Alachiotis, A.P. Kakarountas, H. Michail, G. Panagiotakopoulos, and CE Goutis.
IET Computers & Digital Techniques (CDT) pages 109-123, 2009.
[VLSI-SOC] A Scratch-Pad Memory Accelerator for Exploiting Run-Time Reuse A. Milidonis, V. Porpodas, H. Michail, A.P. Kakarountas, G. Panagiotakopoulos and CE Goutis.
[DATE] A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy. A. Milidonis, N. Alachiotis, V. Porpodas, H. Michail, AP Kakarountas, and CE Goutis.
Design, Automation & Test in Europe (DATE), pages 1-6, 2007.
Some of my spare-time projects:
- slackdesc Slackware package description generator.
- txt2bind Converts simple txt files to BIND compatible configuration files.
- moufoplot A powerful but easy to use gnuplot front-end.