I'm currently pursuing a PhD at the University of Edinburgh, in the School of Informatics, under the supervision of Dr. Vijayanand Nagarajan. I am a member of the Institute for Computing Systems Architecture, and part of the Compiler and Architecture Design Group.
A link to my old website
Research Interests
- HW/SW collaborative techniques for enhancing Performance, Reliability and Security of Multicore processors and Embedded processors.
- FPGA based Accelerators
- Low Power System Design
Publications
- R. Bharghava , R. Abinesh, Suresh Purini, and R. Govindatajulu, (2010), "Design of Low Power Systems Using Inexact Logic Circuits", To appear in the Journal of Low Power Electronics, Vol. 6, No. 3, October 2010 [pdf]
- Bharghava, R.; Abinesh, R.; Purini, S.; Regeti, G.; , "Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting," VLSI Design, 2010. VLSID '10. 23rd International Conference on , vol., no., pp.158-163, 3-7 Jan. 2010. [pdf]
- Abinesh, R.; Bharghava, R.; Purini, S.; Regeti, G.; , "Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer," VLSI Design, 2010. VLSID '10. 23rd International Conference on , vol., no., pp.164-169, 3-7 Jan. 2010. [pdf]
- Abinesh R., Bharghava R., M.B. Srinivas, "Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication," ISVLSI, pp.103-108, 2009 IEEE Computer Society Annual Symposium on VLSI, 2009. [pdf]
- Bharghava, Jyothish Soman, K S Rajan, "Applicability and Performance of Cell BE as a Mobile GIS High Performace Platform", Joint International Workshop of ISPRS WG IV/1, WG VIII/1 and WG IV/3 on Geospatial Data Cyber Infrastructure and Real-time Services with special emphasis on Disaster Management, November 25-27, 2009, Hyderabad,India. [ppt]
- Bharghava R, Jyothish Soman, K S Rajan, "Parallelizing GIS applications for IBM Cell Broadband engine and Intel multicore platforms", FOSS4G 2009, Sydney. [poster]
Internship
- Interned at Xilinx Research Labs, Hyderabad, India, under the guidance of Dr. Chidamber Kulkarni from February - July, 2010.
Worked on High Level Synthesis of Network Processing Elements targetting NetFPGA & Xilinx EPP.
Awards
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