Contact

Address:
The University of Edinburgh
IF 1.25
Informatics Forum
10 Crichton Street
Edinburgh, EH8 9AB

E-mail:

cheng-chieh.huang [at] ed.ac.uk

I am pursuing a PhD (since 2011) in the School of Informatics at the University of Edinburgh, under the supervision of Vijay Nagarajan. I am a member of the Institute for Computing Systems Architecture.
Memory systems, hardware/software co-design, processor architecture.
Teaching Assistant: Parallel Architecture (University of Edinburgh), 2014.
  • C. Huang and V. Nagarajan, Increasing Cache Capacity via Critical-words-Only Cache, The 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, October 2014.
  • C. Huang and V. Nagarajan, ATCache: Reducing DRAM Cache Latency via a Small SRAM Tag Cache, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Edmonton, Canada, August 2014.