A am a first year PhD student in CDT in Pervasive Parallelism. This Centre for Doctoral Training (CDT) is a combined MSc+PhD program that allows students to dive into a 4 year research project of interest.
My research project focuses on enabling fast multi-core hardware simulation.
High-Level Synthesis of Functional Patterns with Lift
June 2019 - PLDI - ARRAY 2019
Publishing result of work done in BSc Thesis below. Additional optimisations are introduced.
Mitigating JIT Compilation Latency in Virtual Execution Environments
Apr 2019 - Virtual Execution Environments 2019
Publishing results of work done in MSc Thesis below.
Compilation Scheduling Policy for JIT-Based Systems
Aug 2018 - MSc Thesis
Just-in-Time compilation is the key technology for fast cross-architecture simulation. The best results are observed when the compilation itself is offloaded to a background thread. This thesis concerns policies used to order compilation units in a compilation queue. This schedule has a major impact on the final performance of the whole system.
High-Level Synthesis of Functional Patterns for Reconfigurable Logic
May 2017 - BSc Thesis
Reconfigurable Logic (FPGA) has great performance and energy advantages compared to traditional CPUs. However, it is extremely hard to program. Lift framework alleviates this problem by exposing a high-level functional programming language. This project creates a back-end to the Lift compiler targeting FPGA. Simple matrix multiplication expression can be compiled to data-flow hardware design.
- 3.04 Bayes Centre, The University of Edinburgh
47 Potterrow, Edinburgh EH8 9BT