Picture of me

Timothy M. Jones

Institute for Computing Systems Architecture
School of Informatics
1.12 Informatics Forum
10 Crichton Street
Edinburgh
EH8 9AB

0131 650 3092

tjones1@inf.ed.ac.uk

PhD: The University of Edinburgh, 2006.

Royal Academy of Engineering / EPSRC Research Fellow (2008 - 2013)


Hello!

I'm a post-doctoral researcher here at the University of Edinburgh in the School of Informatics. From 1 September 2008 I hold a Research Fellowship from the Royal Academy of Engineering and EPSRC. I work in the Compiler and Architecture Design Group and in collaboration with other researchers throughout Europe. I was previously coordinator of the compiler workpackage in the SARC project, funded by the European Union under the 6th Framework Programme. I am currently also technical leader of the adaptive compilation cluster in the HiPEAC2 network of excellence.


Research

My research is looking at ways of using the compiler to adapt the hardware. My PhD thesis considered energy savings in superscalar processors and using the compiler to give hints to the processor about the resources needed for the next few instructions. The compiler, of course, has the advantage that it knows a bit about the future. I considered the issue queue and register file for optimisation. For an overview of some research, take a look at this poster. My current research areas include:

I am interested in collaborations with other researchers on any of the above. If you would like to work with me then please send me an email.

In my spare time I play the trombone in orchestras and bands around Edinburgh, along with my quintet.


PhD Students

I'm currently recruiting PhD students for the following projects. If you are intested, please send me an email.

Energy and Thermal-Aware Cache Optimisation

In any modern architecture, the cache hierarchy occupies a significant fraction of the total chip area and thus consumes a large amount of energy. It is also the first point in any multi-core system where threads will interact with each other. The differing requirements of these threads can be lead to sub-optimal cache performance and energy consumption. This project will focus on the use of the compiler and runtime solutions to optimise the cache hierarchy for power reduction and thermal management.


Professional Service


Publications


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