Vijay Nagarajan Image Vijay Nagarajan

Reader (Associate Professor)
Institute of Computer Systems Architecture
School of Informatics
University of Edinburgh
1.22 Informatics Forum
10 Crichton Street
Edinburgh, EH8 9AB

Office Phone: (+44) 131-651-3440
E-mail: vijay.nagarajan at ed.ac.uk
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Publications

Patents


Publications

2018

[ASPLOS] R. Kumar, B. Grot, and V. Nagarajan
Blasting Through The Front-End Bottleneck with Shotgun
The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems, March 2018.
[DATE] M. Elver, C. J. Banks, P. Jackson, and V. Nagarajan
VerC3: A Library for Explicit State Synthesis for Concurrent Systems
Design, Automation and Test in Europe, March 2018 (to appear).
2017

[FMCAD] C. J. Banks, M. Elver, R. Hoffmann, S. Sarkar, P. Jackson, and V. Nagarajan
Verification of a lazy cache coherence protocol against a weak memory model (preprint)
The 17th Conference on Formal Methods in Computer-Aided Design, Oct 2017 (to appear).
[Code]
[ISPASS] S. Dublish, V. Nagarajan and N. Topham
Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs
IEEE International Symposium on Performance Analysis of Systems and Software
San Francisco, April 2017.
[HPCA] A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas
ATOM: Atomic Durability in Non-volatile Memory through Hardware Support for Logging
The 23rd IEEE Symposium on High Performance Computer Architecture
Austin, Texas, USA Feb 2017.
[HPCA] R. Kumar, C. Huang, B. Grot, and V. Nagarajan
Boomerang: a Metadata-Free Architecture for Control Flow Delivery
The 23rd IEEE Symposium on High Performance Computer Architecture
Austin, Texas, USA Feb 2017.
[TACO] S. Dublish, V. Nagarajan and N. Topham
Cooperative Caching for GPUs
ACM Transactions on Architecture and Code Optimization
Also invited presentation at HiPEAC 2017, Stockholm, Sweden, Jan 2017.
2016

[MICRO] C. Huang, R. Kumar, M. Elver, B. Grot, and V. Nagarajan
C3D: Mitigating NUMA Effects via Coherent DRAM Caches
The 49th ACM/IEEE International Symposium on Microarchitecture,
Taipei, Taiwan, October 2016.
[C3D Specification and Murphi Model]
[SC] C. Huang, V. Nagarajan and A. Joshi
DCA: a DRAM-cache-aware DRAM controller
The IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis,
Salt Lake City, USA November 2016.
[IROS] J. Cano, A. Bordallo, V. Nagarajan, S. Ramamoorthy, and S. Vijayakumar
Automatic Configuration of ROS Applications for near-optimal Performance
IEEE/RSJ International Conference on Intelligent Robots and Systems
Korea, October 2016 (to appear).
[RSS] J. Cano, D. White, A. Bordallo, C. McCreesh, P. Prosser, J. Singer and V. Nagarajan
Task Variant Allocation in Distributed Robotics
Robotics: Science and Systems
Ann Arbor, USA, June 2016.
[Code]
[HPCA] M. Elver and V. Nagarajan
McVerSi: A Test Generation Framework for Fast Memory Consistency Verification in Simulation
The 22nd Symposium on High Performance Computer Architecture
Barcelona, Spain March 2016.
[Simulator-independent library]
[TACO] A. J. McPherson, V. Nagarajan, S. Sarkar and M. Cintra
Fence placement for legacy data-race-free programs via synchronization read detection
ACM Transactions on Architecture and Code Optimization, January 2016.
Also appeared as PPoPP Poster, Feb 2015.
2015

[MICRO] A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas
Efficient Persist Barriers for Multicores
The 48th Annual IEEE/ACM International Symposium on Microarchitecture
Waikiki, Hawaii, USA Dec 2015.
[PACT] M. Elver and V. Nagarajan
RC3: Consistency directed Cache Coherence for x86-64 with RC extensions
The 24th International Conference on Parallel Architectures and Compilation Techniques
San Francisco, USA Oct 2015.
[SAFECOMP] G. Stefanakis, V. Nagarajan, and M. Cintra
Understanding the Effects of Data Corruption on Application Behavior Based on Data Charecterestics
International Conference on Computer Safety, Reliability and Security
Delft, Netherlands Sep 2015.
[ICAR] J. Cano, E. Molinos, V. Nagarajan, and S. Vijayakumar
Dynamic process migration in heterogeneous ROS-based environments
The 17th International Conference on Advanced Robotics
Istanbul, Turkey July 2015.
[NVMW] M. Cintra, A. Chatzistergiou, A. Joshi, V. Nagarajan, and S. Viglas
DAPPER: a database-inspired approach to persistent memory
Non-Volatile Memories Workshop
San Diego, USA March 2015.
2014

[SC] C. Lin, V. Nagarajan and R. Gupta
Fence Scoping
The IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis,
New Orleans, USA November 2014.
[ICCD] C. Huang and V. Nagarajan
Increasing Cache Capacity via Critical-words-Only Cache
The 32nd IEEE International Conference on Computer Design,
Seoul, Korea October 2014.
[LCPC] A. J. McPherson, V. Nagarajan, and M. Cintra
Static Approximation of MPI Communication Graphs for Optimized Process Placement
The 27th International Workshop on Languages and Compilers for Parallel Computing,
Hilsboro, September 2014.
[PACT] C. Huang and V. Nagarajan
ATCache: Reducing DRAM cache Latency via a Small SRAM Tag Cache
The 23rd International Conference on Parallel Architectures and Compilation Techniques,
Edmonton, Canada, August 2014.
[HPCA] M. Elver and V. Nagarajan
TSO-CC: Consistency directed cache coherence for TSO
The International Symposium on High-Performance Computer Architecture,
Orlando, USA Feb 2014.
[TSO-CC Specification]
2013

[PLDI] B. Rajaram, V. Nagarajan, S. Sarkar, and M. Elver
Fast RMWs for TSO: Semantics and Implementation
ACM SIGPLAN Conference on Programming Language Design and Implemenation,
Seattle, Washington, June 2013.
[ICS] C. Lin, V. Nagarajan, and R. Gupta
Address-aware Fences
27th International Conference on Supercomputing,
Eugene, Oregon, June 2013
2012

[ACM CF] B. Rajaram, V. Nagarajan, A. J. McPherson, and M. Cintra
SuperCoP: A General, Correct, and Performance-efficient Supervised Memory System,
ACM International Conference on Computing Frontiers,
May 2012.
[ASPLOS] C. Lin, V. Nagarajan, R. Gupta and B. Rajaram
Efficient Sequential Consistency via Conflict Ordering,
ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems,
March 2012.
[ASPLOS poster] Received 2nd prize: Best Poster
B. Rajaram and V. Nagarajan
Fast RMWs for TSO,
ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems,
Poster session.
2011

[SP&E] V. Nagarajan, D.Jeffrey, and R.Gupta
A System for Debugging via Online Tracing and Dynamic Slicing,
Software - Practice & Experience,
July 2011.
[IJPP] C.Lin, V. Nagarajan, and R.Gupta
Efficient Sequential Consistency Using Conditional Fences,
International Journal of Parallel Programming,
June 2011.
2010

[PACT] Received a Best Paper Award
C.Lin, V. Nagarajan, and R.Gupta
Efficient Sequential Consistency Using Conditional Fences,
The 19th International Conference on Parallel Architectures and Compilation Techniques,
Vienna, Austria, September 2010.
[TOPLAS] D.Jeffrey, V. Nagarajan, and R.Gupta
Execution Supression: An Automated Iterative Technique for locating Memory Errors,
ACM Transactions on Programming Languages and Systems,
Vol. 32, No. 5, 36 pages, May 2010.
2009

[LCPC] V. Nagarajan and R.Gupta,
Speculative Optimizations for Parallel Programs on Multicores,
22nd International Workshop on Languages and Compilers for Parallel Computing,
Newark, Delaware, October 2009.
[IJPP] C. Tian, M.Feng, V. Nagarajan and R. Gupta,
Speculative Parallelization of Sequential Loops On Multicores,
International Journal of Parallel Programming, October 2009.
[SP&E] C. Tian, V. Nagarajan, R. Gupta, and S. Tallam,
Automated Dynamic Detection of Busy-wait Synchronizations,
Software - Practice and Experience, August 2009.
[ISCA] V. Nagarajan and R.Gupta,
ECMon: Exposing Cache Events for Monitoring,
ACM/IEEE 36th International Symposium on Computer Architecture,
Austin, Texas, June 2009.
[ISMM] V. Nagarajan, D. Jeffrey and R. Gupta,
Self Recovery in Server Programs,
International Symposium on Memory Management,
Dublin, Ireland, June 2009.
[SIGOPS] V. Nagarajan and R.Gupta,
Runtime Monitoring on Multicores via OASES,
ACM SIGOPS Operating Systems Review,
special issue on the interaction among the OS, Compilers, and Multicore Processors,
10 pages, April 2009 (Invited Paper).
[VEE] V. Nagarajan and R.Gupta,
Architectural Support for Shadow Memory in Multiprocessors,
ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments,
10 pages, Washington DC, March 2009.
[Trans. HiPEAC] V.Nagarajan, R. Gupta, and A.Krishnaswamy,
Compiler-Assisted Memory Encryption for Embedded Processors
Transactions on High Performance Embedded Architectures and Compilers,
Vol. 2, No. 1, pages 23-44, Springer Verlag, 2009
(Invited Paper -- special issue of selected papers from HiPEAC Conference).

2008

[MICRO] C. Tian, M. Feng, V. Nagarajan, and R. Gupta,
Copy or Discard Execution Model For Speculative Parallelization On Multicores,
IEEE/ACM 41st International Symposium on Microarchitecture,
pages 330-341, Lake Como, Italy, Nov. 2008.
[ISSTA] C. Tian, V. Nagarajan, R. Gupta, and S. Tallam,
Dynamic Recognition of Synchronization Operations for Improved Data Race Detection,
SIGSOFT International Symposium on Software Testing and Analysis,
pages 143-154, Seattle, July 2008.
[PADTAD] V. Nagarajan and R.Gupta,
Support for Symmetric Shadow Memory in Multiprocessors,
Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging,
(colocated with ISSTA), 9 pages, Seattle, July 2008.
[STMCS] C. Tian, V. Nagarajan, and R. Gupta,
Synchronization Aware Conflict Resolution for Runtime Monitoring Using Transactional Memory,
Workshop on Software Tools for Multicore Systems,
(colocated with CGO), 6 pages, Boston, April 2008.
[NSFNGS] R. Gupta, N. Gupta, X. Zhang, D. Jeffrey, V. Nagarajan, S. Tallam and C. Tian
Scalable Dynamic Information Flow Tracking and its Applications,
NSF Next Generation Software Workshop,
colocated with IPDPS, pages 1-5, Florida, April 2008.
[INTERACT] V. Nagarajan, H-S.Kim, Y.Wu and R. Gupta,
Dynamic Information Flow Tracking on Multicores,
Workshop on Interaction between Compilers and Computer Architectures,
(colocated with HPCA), 10 pages, Salt Lake City, Feb. 2008.

2007

[ICSM] V. Nagarajan, D. Jeffrey, R. Gupta and N. Gupta
ONTRAC: A System for Efficient ONline TRACing for Debugging,
International Conference on Software Maintenance,
pages 445-454, Paris, September 2007.
[ICSM] V. Nagarajan, R. Gupta, X. Zhang, M. Madou, and B. De Sutter
Matching Control Flow of Program Versions,
International Conference on Software Maintenance,
pages 84-93, Paris, September 2007.
[HiPEAC] V.Nagarajan, R. Gupta, and A.Krishnaswamy,
Compiler-Assisted Memory Encryption for Embedded Processors
International Conference on High Performance Embedded Architectures and Compilers,
Springer Verlag, LNCS 4367, pages 7-22, Ghent, Belgium, January 2007.

Patents