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Vijay Nagarajan Lecturer (Assistant Professor) Institute of Computer Systems Architecture School of Informatics University of Edinburgh 1.22 Informatics Forum 10 Crichton Street Edinburgh, EH8 9AB Office Phone: (+44) 131-651-3440 E-mail: vijay.nagarajan at ed.ac.uk |
Back to Home Publications Patents |
| Publications |
| 2013 |
| [PLDI] |
B. Rajaram, V. Nagarajan, S. Sarkar, and M. Elver Fast RMWs for TSO: Semantics and Implementation ACM SIGPLAN Conference on Programming Language Design and Implemenation, Seattle, Washington, June 2013. |
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| [ICS] |
C. Lin, V. Nagarajan, and R. Gupta Address-aware Fences 27th International Conference on Supercomputing, Eugene, Oregon, June 2013 |
| 2012 |
| [ACM CF] |
B. Rajaram, V. Nagarajan, A. J. McPherson, and M. Cintra SuperCoP: A General, Correct, and Performance-efficient Supervised Memory System, ACM International Conference on Computing Frontiers, May 2012. |
| [ASPLOS] |
C. Lin, V. Nagarajan, R. Gupta and B. Rajaram Efficient Sequential Consistency via Conflict Ordering, ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems, March 2012. |
| [ASPLOS poster] |
Received 2nd prize: Best Poster B. Rajaram and V. Nagarajan Fast RMWs for TSO, ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems, Poster session. |
| 2011 |
| [SP&E] |
V. Nagarajan, D.Jeffrey, R.Gupta and N.Gupta A System for Debugging via Online Tracing and Dynamic Slicing, Software - Practice & Experience, July 2011. |
| [IJPP] |
C.Lin, V. Nagarajan, and R.Gupta Efficient Sequential Consistency Using Conditional Fences, International Journal of Parallel Programming, June 2011. |
| 2010 |
| [PACT] |
Received a Best Paper Award C.Lin, V. Nagarajan, and R.Gupta Efficient Sequential Consistency Using Conditional Fences, The 19th International Conference on Parallel Architectures and Compilation Techniques, Vienna, Austria, September 2010. |
| [TOPLAS] |
D.Jeffrey, V. Nagarajan, R.Gupta and N.Gupta Execution Supression: An Automated Iterative Technique for locating Memory Errors, ACM Transactions on Programming Languages and Systems, Vol. 32, No. 5, 36 pages, May 2010. |
| 2009 |
| [LCPC] |
V. Nagarajan and R.Gupta, Speculative Optimizations for Parallel Programs on Multicores, 22nd International Workshop on Languages and Compilers for Parallel Computing, Newark, Delaware, October 2009. |
| [IJPP] |
C. Tian, M.Feng, V. Nagarajan and R. Gupta, Speculative Parallelization of Sequential Loops On Multicores, International Journal of Parallel Programming, October 2009. |
| [SP&E] |
C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Automated Dynamic Detection of Busy-wait Synchronizations, Software - Practice and Experience, August 2009. |
| [ISCA] |
V. Nagarajan and R.Gupta, ECMon: Exposing Cache Events for Monitoring, ACM/IEEE 36th International Symposium on Computer Architecture, Austin, Texas, June 2009. |
| [ISMM] |
V. Nagarajan, D. Jeffrey and R. Gupta, Self Recovery in Server Programs, International Symposium on Memory Management, Dublin, Ireland, June 2009. |
| [SIGOPS] |
V. Nagarajan and R.Gupta, Runtime Monitoring on Multicores via OASES, ACM SIGOPS Operating Systems Review, special issue on the interaction among the OS, Compilers, and Multicore Processors, 10 pages, April 2009 (Invited Paper). |
| [VEE] |
V. Nagarajan and R.Gupta, Architectural Support for Shadow Memory in Multiprocessors, ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 10 pages, Washington DC, March 2009. |
| [Trans. HiPEAC] |
V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors Transactions on High Performance Embedded Architectures and Compilers, Vol. 2, No. 1, pages 23-44, Springer Verlag, 2009 (Invited Paper -- special issue of selected papers from HiPEAC Conference). |
| 2008 |
| [MICRO] |
C. Tian, M. Feng, V. Nagarajan, and R. Gupta, Copy or Discard Execution Model For Speculative Parallelization On Multicores, IEEE/ACM 41st International Symposium on Microarchitecture, pages 330-341, Lake Como, Italy, Nov. 2008. |
| [ISSTA] |
C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Dynamic Recognition of Synchronization Operations for Improved Data Race Detection, SIGSOFT International Symposium on Software Testing and Analysis, pages 143-154, Seattle, July 2008. |
| [PADTAD] |
V. Nagarajan and R.Gupta, Support for Symmetric Shadow Memory in Multiprocessors, Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, (colocated with ISSTA), 9 pages, Seattle, July 2008. |
| [STMCS] |
C. Tian, V. Nagarajan, and R. Gupta, Synchronization Aware Conflict Resolution for Runtime Monitoring Using Transactional Memory, Workshop on Software Tools for Multicore Systems, (colocated with CGO), 6 pages, Boston, April 2008. |
| [NSFNGS] |
R. Gupta, N. Gupta, X. Zhang, D. Jeffrey, V. Nagarajan, S. Tallam and C. Tian Scalable Dynamic Information Flow Tracking and its Applications, NSF Next Generation Software Workshop, colocated with IPDPS, pages 1-5, Florida, April 2008. |
| [INTERACT] |
V. Nagarajan, H-S.Kim, Y.Wu and R. Gupta, Dynamic Information Flow Tracking on Multicores, Workshop on Interaction between Compilers and Computer Architectures, (colocated with HPCA), 10 pages, Salt Lake City, Feb. 2008. |
| 2007 |
| [ICSM] |
V. Nagarajan, D. Jeffrey, R. Gupta, and N. Gupta, ONTRAC: A System for Efficient ONline TRACing for Debugging, International Conference on Software Maintenance, pages 445-454, Paris, September 2007. |
| [ICSM] |
V. Nagarajan, R. Gupta, X. Zhang, M. Madou, B. De Sutter, and K. De Bosschere, Matching Control Flow of Program Versions, International Conference on Software Maintenance, pages 84-93, Paris, September 2007. |
| [HiPEAC] |
V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors International Conference on High Performance Embedded Architectures and Compilers, Springer Verlag, LNCS 4367, pages 7-22, Ghent, Belgium, January 2007. |
| Patents |
Software Flow Tracking using Multiple threads.
Inventors: V. Nagarajan, H-S. Kim (Intel), Y. Wu (Intel), and R. Gupta, US Patent 8,321,840 .