PAMELA (A Panoramic View of the Many-core Landscape) is an EPSRC-funded project investigating the design of computer systems and algorithms for next-generation computer vision applications. The project is a collaboration between the University of Edinburgh, Imperial College London, and The University of Manchester, and investigates the architectures, algorithms, and run-time systems which might be required for applications domains such as augmented and mixed reality, robotics, and autonomous vehicles.
I am currently working on the PAMELA project, an EPSRC-funded project investigating architectures and systems for computer vision. My main interests are in Dynamic Binary Translation, Architecture Description Languages, and High Speed Simulation.
GenSim is an architecture description language and tool set for producing high speed instruction set simulators from a high level architecture description. The semantics of the instructions are described using a C-like language which can be easily analysed and a high performance JIT compiler frontend is produced. GenSim is capable of producing simulation tools which can run at 100s to 1000s of MIPS (Millions of Instructions Per Second), far faster than a conventional hand-written simulator.
Typically, the performance of a simulator is evaluated by running standard benchmark suites such as SPEC or EEMBC. Although these are capable of representing real-world use cases, it is difficult to identify specific performance bottlenecks or perform a detailed performance evaluation. Conversely, standard microbenchmark approaches are typically ad-hoc and often do not take a holistic view of the simulator, and so potentially miss unexpected performance degradations. SimBench is designed to solve this problem. It consists of 18 individual benchmarks in 5 categories, and targets full-system simulators. SimBench is easy to port to new architectures and platforms, and is easy to use.
In order to perform basic tests of the developed GenSim architectural models, I have also developed a basic instruction fuzzer. This fuzzer takes easy-to-write assembly templates (which can include complex constant value generators), and produces inputs to a test harness. Generators and test harnesses are available for a variety of architectures, and it is easy to write new ones.