The low cost of the DAP was partially attributable to the use of conservative technology, although the method of connecting the DAP to its host processor certainly played an important part as well. The DAP was essentially a co-processor, marketed as an add-on to an ICL 2900 mainframe. The memories of the DAP processing elements were configured so that they appeared, from the host's perspective, to be simply an additional memory segment. The host therefore had full read/write access to the distributed memory within the processor array.
The architecture and technology of a machine can rarely be considered in isolation; more often than not technology is a limiting factor for the computer architect, effectively dictating what can or cannot be implemented at a reasonable cost. Occasionally, new technology gives rise to new architecture, rendering previously unimplementable structures feasible. Some of the most successful high-performance machines, particularly those designed by Seymour Cray, have been supported by such technology-driven advances. The DAP however is different, and was, in its day, one of the most technology-independent of all high performance architectures. This stems from the relatively low clock rate of 5 MHz, and the use of massive data-parallelism as a means of achieving high performance in preference to using very high speed logic and a pipelined architecture.