The overall design of the 7600 is in many ways similar to that of the 6600. Instructions are fetched from the Small Core Memory (SCM) and placed in the 12-word Instruction Stack before being copied into the Current Instruction Word (CIW) register for decoding and issue to one of the nine functional units. The control logic associated with the CIW register (see under Instruction Buffers) serves the same purpose as the Scoreboard in the 6600, but is somewhat less complex. On early models of the 7600 the SCM consisted of either 32K or 64K words of 275 ns cycle-time core store made up from 16 or 32 independent 2K word banks. On current models the SCM consists of either 64K or 128K words of semiconductor memory made up from 32 or 64 independent 4K word banks. Although quite different internally these memories appear virtually identical to the rest of the system and because of the interleaving both can transfer sequentially addressed data at a rate of one word every 27.5 ns.
All instruction accesses and most operand accesses are made to the SCM, and the SCM also communicates with the Large Core Memory (LCM) and with external devices through the Peripheral Processors. The LCM serves as a first level of backing store for the SCM, with blocks of code and data being exchanged between these two, when required, under direct program control. The LCM consists of 256K or 512K 60-bit words in four or eight banks of 1760 ns, word-organised (2D) core store. Each bank operates independently and is eight words wide; once an access has been made to a particular bank the data read out remains available in an output buffer until a subsequent access is made to the same bank. In an eight-bank model this arrangement allows words to be accessed at a rate of 64 per LCM cycle. This time (1760 ns) is equal to 64 minor cycle clock periods, and block copy operations between the LCM and the SCM (in which LCM banks are accessed sequentially) can therefore proceed at the SCM maximum transfer rate of one word per minor cycle.