Functional units in the CDC 7600
Most of the functional units in the CDC 7600 perform identical
functions to those in the 6600. The pipelining of 7600 units obviates
the need for the duplication of units found in the 6600, however, and
control transfers are dealt with by the control logic associated with
the CIW register rather than in a separate Branch unit. Two extra
units are included, since the normalise operation is carried out in a
separate unit from the shift operations, and a separate Population
unit is used to carry out the population count function. In the 6600
this function was implemented within the Divide Unit.
Boolean, Fixed Add, Shift and Increment Units
The Boolean, Fixed Add, Shift and Increment Units in the 7600 carry
out similar operations to those in the equivalent units in the 6600,
but each is pipelined into two stages. Input operands are copied into
one of these units at the start of one minor cycle clock period, and a
second pair of operands may be copied in at the start of the next
minor cycle. At the end of this second minor cycle the result of the
first operation is copied into the designated result register.
Floating Add Unit
The Floating Add Unit operates as a four-stage pipeline, but in
comparison with the TI ASC arithmetic pipeline the partitioning is
expedient rather than elegant. Thus whereas the TI ASC pipeline
consists of a number of functionally distinguishable sections, the
pipeline stages in the 7600 Floating Add Unit each contain as much
logic as can be accommodated, in terms of logic gate delays, within
one clock period. The mantissa shifting logic and the mantissa adder,
for example, are each split between successive pipeline stages. It is
interesting to note that although a new floating-point addition can be
started at each minor cycle clock period, the time for any one
addition occupies four minor cycles, just as in the 6600.
Floating Multiply Unit
In the 6600 Multiply Unit the mantissa multiplier was split into two
parts, each of which carried out a 24-bit by 48-bit multiplication.
The results of these two parallel operations were then combined to
form a 96-bit product. The 7600 Multiply Unit contains the equivalent
of only one of these half multipliers, and this is used twice in a
two-pass mode of operation. In the first pass the lower 24 bits of Xj
are multiplied by all 48 bits of Xk to form a partial product. This
result is then shifted right 24 places and fed back into the
multiplier to be combined with the result of multiplying the upper 24
bits of Xj by all 48 bits of Xk in the second pass. Thus although the
Multiply Unit is pipelined in a similar fashion to the other
functional units in the 7600, and clocked at every minor cycle clock
period, a new multiplication can only be started in every alternate
clock period. The total time for any one multiplication is 5 minor
cycles, representing a factor of two improvement over the 6600
Multiply Units, each of which took 10 minor cycles to complete a
multiplication.
Divide Unit
Floating-point division is executed by a repeated subtract and test
algorithm which cannot be pipelined. This operation therefore has a
very much longer execution time than any other operation, amounting to
20 minor cycles. A second division can, however, be started 18 minor
cycles after the start of a previous division.
Normalise Unit
Normalisation is carried out in a separate functional unit in the
7600, rather than within the Shift Unit as in the 6600. This is
because normalisation requires a three-stage pipeline, while shifting
and mask generation can be carried out in a two-stage pipeline.
Population unit
The population count function counts the number of ones in the operand
taken from Xk and returns this number as a result to Xi. In the 6600
this operation was carried out by hardware contained within the Divide
Unit, but since it only requires two clock periods for its execution,
a separate Population Count Unit, implemented as a two-stage pipeline,
is used for this purpose in the 7600.