The SLIC

In the SB8000, every processor, memory controller, I/O channel and bus controller has associated with it a System Link and Interrupt Controller (SLIC) chip. The SLIC is effectively a coprocessor providing the functions required in a shared-memory multiprocessor, but not at the time present in commercially available microprocessors (such as the NS32032). In addition to providing these extra functions, the SLIC also contributes to the parallelism in the system by operating independently from the system bus.

The functions of the SLIC are three-fold. Firstly, between them the SLIC devices manage the distribution of incoming interrupts, and they do this by dynamically assigning each interrupt to the processor which is currently executing the lowest priority task. In order to organise the distribution, all controllers communicate with each other across a dedicated serial bus, somewhat similar in operation to an Ethernet. The structure of a SLIC chip, and its connections to the SLIC bus, are shown in the figure. It is interesting to note that some of the most time-critical functions of this shared-memory architecture are actually implemented within a message-passing multiple-coprocessor sub-system, and not through the shared memory.

The second function of the SLIC, and another time-critical function, is the manipulation of system-wide semaphores. As shown in the figure, each SLIC contains a cache of semaphores. Effectively these are single-bit protection flags, through which all high-level mutual exclusion and synchronisation facilities are implemented. An important consequence of implementing processor synchronisation primitives with dedicated hardware is that spin-lock operations do not need to access global memory via the system bus. Spin-locks can present quite a heavy load on the system bus, and therefore any technique which removes this load must improve the performance of the whole system. Note however, that this migration of functionality can only improve memory bandwidth, and cannot solve the performance problem caused by the busy waiting which occurs during spin-lock operations.

The third function of the SLIC is to act as a supervisory agent and communicate with other SLICs to perform system diagnostics and debugging. It can, for example, take the resources for which it is responsible off-line and notify the system. Similarly, when a new processor card is inserted, the SLIC informs the other resources via the SLIC bus, and the system automatically re-configures itself without further physical modification.

The SLIC chip is implemented using 3μM CMOS gate-array technology, and the SLIC bus is implemented as a two-wire multi-drop serial link using wired-OR logic and incorporating collision-detect circuitry. The SLIC represents a very useful innovation, contributing heavily towards the efficient engineering of the sequentially accessed shared-memory of the SB8000. The other major component is of course the system bus.