The Sequent Balance 8000

The constraining nature of the common-bus multiprocessor architecture stimulates the ingenuity of designers, who then produce sophisticated solutions. The Sequent Balance is a good example of this phenomenon, as it incorporates special techniques for providing very high bus bandwidth as well as for supporting primitive locking operations.

The designers of the SB8000 started out with the knowledge that, in previous multiprocessor systems, each additional processor contributed only 0.8 x the actual performance of each processor already in the system. Hence, points on the speedup curve for such a system would typically be 1, 1.8, 2.5, ... This diminishing return made each successive processor less and less cost effective. This means that careful engineering of the critical components is required in order to alleviate this problem.

The SB8000 system is a homogeneous multiprocessor system, capable of supporting between two and twelve identical processors, based on the National Semiconductors NS32032 32-bit microprocessor. Each processor is supplied with a floating-point coprocessor and memory management hardware. All processors share a number of common memory modules via a 26.7 Mbyte/s system bus, providing up to 28 Mbytes of primary storage. All processors share a single copy of the Unix-like operating system and, in order to reduce global memory contention, each processor has a private cache for storing recently used instructions and data. This is a two-way set-associative cache with an 8 Kbyte capacity. Transfers between main memory and the cache occur in units of 64 bits, yielding an effective hit-ratio of 95 per cent.

The SB8000 has an orthogonal architecture, which means that all memory, I/O and interrupt resources are accessible to all processors. These resources are allocated dynamically. Hence, a process scheduler assigns processors from the pool of processing resources, earning it the title "processor pool" architecture. The fair distribution of work requires careful hardware and software design to ensure that there is good utilisation of all resources, especially the pool of processors. Central to this theme is a custom coprocessor chip, known as the System Link and Interrupt Controller (SLIC), which is optimised to perform tasks which normally cripple the performance of less sophisticated bus-structured multiprocessors.