The MU5 Name Store

In the late 1960s a quite different approach to high-speed buffering was taken in the design of the MU5 computer. The use of fast programmable registers in MU5 was rejected in favour of a small associatively addressed buffer store containing only named scalar variables and forming part of a one-level store with the Local Store of the processor [1], [2]. Simulation studies of this Name Store indicated that a hit-rate of around 99 per cent would be obtained with 32 words of store, a number which it was technologically and economically feasible to construct and operate at a 50 ns rate, and which could be conveniently fitted on to two of the platters used in the construction of MU5.

Thus the address and value fields of the Name Store (see figure) each occupy one of these platters, and form two adjacent stages of the Primary Operand Unit (PROP) pipeline, through which instructions move in a series of beats (see under Pipelines). At each beat a virtual address generated in the previous two stages of the pipeline is copied into the Interrogate Register (IN), and concatenated with the contents of the Process Number register (PN), for presentation to the address field of the Name Store. A full virtual address in MU5 consists of a 4-bit Process Number, a 14-bit Segment and 16 bits which identify a 32-bit word within a segment. Addresses presented to the Name Store do not contain the Segment Number, however, since it was assumed at the design stage that the Name Segment would always be zero, and only 15 of the word address bits are used, referring to 64-bit operands. Where necessary, a 32-bit operand is selected from within a 64-bit word in a later stage of the pipeline.