The CRAY X-MP

The first CRAY-1 was delivered in 1976 and shortly after that Seymour Cray began a development effort aimed at producing a significantly more powerful system, the Cray-2 (q.v.). In mid 1979, however, a separate group within Cray Research started work on the design of a system which would have an essentially identical instruction set to the CRAY-1 but considerably more power. The possibility of obtaining this power by adding more vector units was considered, but although improved vector performance was obviously important, improved scalar performance was seen to be more important. A deliberate decision was therefore made to pursue a multiprocessor design rather than one involving multiple vector units. The prototype two-processor version of this system, the CRAY X-MP/2, [1], [2], [3] became operational early in 1982. Following this a four-processor version and a single processor version appeared in rapid succession. The multiprocessor versions not only offer improved overall throughput for single-process jobs in a time-sharing environment but the FORTRAN compiler has an auto partitioning capability which allows it to generate object code which utilises multiple processors within a single job whenever possible.

The X-MP range of computer systems now includes models with one, two or four processors and memory options of 1, 2, 4, 8 or 16 million (64-bit) words. The memory is organised as 16, 32 or 64 interleaved banks, according to size, and all banks can be accessed independently and in parallel in each clock cycle (see under Central memory organisation). This Central Memory is shared by all processors, as shown in the figure, which shows the overall organisation and major data paths of the X-MP/4.

The processors (CPU0 - CPU3) communicate with each other through shared access to clusters of communication registers (CR), and with peripheral devices through shared input-output (I/O) ports. I/O can be initiated by any processor and any processor can in principle deal with any interrupt. In practice I/O interrupts are handled by whichever processor happens to be running the operating system at the time of an interrupt, or, if no processor is running the operating system, by the initiating processor.

The input-output subsystem (IOS) itself contains two or four peripheral processors. The IOS communicates with central memory through one (or in some models two) channels, each having a burst transfer rate of 100 Mbytes/s, with a (possible) variety of front-end computer systems and with peripherals such as disc units and magnetic tape drives. The (optional) Solid-state Storage Device (SSD) is a random access secondary storage device which can be treated as a disc for job swapping and for storing non-permanent files. It has a storage capacity of between 256 Mbytes and 4 Gbyte and a 0.4 ms access time. It is connected to central memory by one (or two) channels, each of which has a transfer rate capability of 1 Gbyte/s, one hundred times that of the fastest disc available. There is also an (optional) data path (made up of between one and four 100 Mbyte/s channels) between the IOS and SSD.