Computer Architecture Simulation & Visualisation

EMMA

Edinburgh Microcoded Microprocessor Architecture

When EMMA was originally created in 2005, there were two versions, a basic version (EMMA-1), that could execute simple arithmetic and logic operations, and an enhanced version (EMMA-2), that contained facilities to allow multiplication and division to be implemented in microcode. The current version (EMMA-3) is a revised version of EMMA-2, capable of executing the full EMMA instruction set. The revisions include a change in the way the microinstructions are represented, from an 8-digit hexadecimal value to a string of 8 hexadecimal characters, so as to provide better visualisation.

This website describes the architecture of EMMA-3, its instruction set and microcode, and how to use the model. The files for EMMA-3 can be downloaded from EMMA-3.zip.

Instructions on how to use HASE models can be found at Using HASE Models.

EMMA-3 Processor Architecture

Figure 1. The EMMA-3 simulation model

Words in the Microcode Memory are strucured as follows:

The Label is a string of characters used only for readability purposes.

The Microinstruction is a string of 8 characters representing a set of hexadecimal digits that can be interpreted in one of two different ways according to which half of the 256-word Microcode Memory it is stored in. Microcode words stored in the least significant half of the Microcode Memory are interpreted as being in M-Format, in which two of the hex digits control the Microcode Unit itself, one controls the MPC Unit, one the PC Unit, one the Registers, one the Data Memory and two the ALU. Microcode words stored in the most significant half of the Microcode Memory are interpreted as being in A-Format, in which the hex digit used to control the Data Memory in M-Format is instead used to provide extra control signals for the ALU (see Table 3 below).

The (8-bit integer) Operand field is used for jumps within the microcode memory or as an operand value for some microinstructions. The first 32 locations form a jump table indexed by the Function Number (see Table 2 below), except for locations 0 and 1 which each contain the (one) microcode word needed to implement the JUMP and BRANCH instruction.

EMMA operates on a two phase clock. In clock cycles in which they are active, each unit executes its internal actions in the first phase of the clock and sends out a result packet in the second phase. The Microcode Unit, for example, reads its microcode memory in the first phase and in the second phase sends the appropriate microcode fields to other units, if they are to be activated in the next clock cycle.

The Program Counter and Microprogram Counter units behave identically. They contain the relevant register together with an adder which receives one of its inputs from the register itself and the other from a multiplexer (MPX) which selects either +1 or a value taken from BUS2 in the case of PC or from the Microcode Unit in the case of MPC. (The +1 value is actually an internal connection, the +1 units are just included for visual clarity.) Each has two outputs: Output1, which is connected back to the adder and is permanently enabled, and Output2 which is enabled under microcode control. The bits in the microcode field controlling the Program Counter, for example, activate its inputs and output as follows:

Whenever the PC unit is activated by receipt of a microcode packet in one clock cycle (it should also have received appropriate data packets), it activates the appropriate inputs to the multiplexer and the adder and forms the result in phase 0 of the next clock cycle; in phase 1 of that clock cycle it sends the result of the addition to Output1, back to its own Input1, (always) and to Output2 if the corresponding microcode bit is set.

The buses (BUS1 and BUS2) have a number of input connections but should receive data from only one of them in any one (phase 1) clock period. Inputs which do not receive data are set to zero. The inputs are internally ORed together (simulating a wired-OR bus) and the result is sent to all the outputs half way through the clock phase in which they were received.

The Data Memory has its own built-in Memory Address Register (MAR) and Memory Buffer Register (MBR). The microcode field controlling the memory is as follows:

For a read operation (Read/Write = 0), the address sent from BUS2 is copied into MAR in the next clock phase 0, the memory is read and the result copied into MBR. In the subsequent clock phase 1, the value in MBR is sent to BUS1. For a write operation (Read/Write = 1), the address sent from BUS2 is copied into MAR in the next clock phase 0, the data value sent from BUS1 is copied into MBR and the value is written into the memory.

The Registers unit contains 16 general purpose registers, with R0 being permanently set to 0. It receives input values from the ALU and has two outputs connected to BUS1 and BUS2. Whenever the Microcode Unit sends a microcode command to the Registers unit, it appends the appropriate source and destination register numbers extracted from the instruction in IR. The microcode field controlling the registers is as follows:

Executing an instruction such as ADD RD RS1 RS2 requires the execution of 3 microinstructions. The first microinstruction reads the values in registers RS1 and RS2 and sends them to BUS1 and BUS2 respectively. This is achieved by setting the Registers field in the microcode word to 0011. The second microinstruction controls the adder, while the third causes the result sent from the adder to the Registers to be written into RD. This microinstruction also increments the Program Counter. If the Swap bit is set, however, then the first microinstruction sends the value in RD to BUS2 instead of RS2 and the third microinstruction writes the result from the adder into RS1. This facility allows for the implementation in microcode of complex instructions such as forming the sum of the first n natural numbers.

The Arithmetic and Logic Unit (ALU) has two data inputs, one each from BUS1 and BUS2. Values received from the buses are loaded into registers A and B. The result of an operation is loaded into the Accumulator (ACC), which has two external outputs, one connected to the Registers Unit and one to BUS2, and one internal connection back into the ALU. When the Microcode Unit sends a microcode command to the ALU, it appends the appropriate function code derived from the instruction in IR. There are two condition code bits: CC0 is set = 0 if the ALU result = 0; CC1 is set = 1 if the ALU result < 0. CC0 and CC1 are directly connected to the Microcode Unit which can use them in condition tests in the clock period after an ALU operation has been executed.

Eight Basic Functions are provided in the ALU, as shown in Table 1 below, together with eight Extra Functions that allow for the implementation of multiplication and division in microcode. Four of these extra functions operate on the A and B registers. The D register is intended for use in counting down the number of cycles during division.

The EMMA Instruction Set

When downloaded, the model files include a MICROCODE.Microcode.mem file that contains microcode for the JUMP and LD instructions. The first 32 locations of the microcode memory are used as a jump table, indexed by the function number (except for location 0, which contains the single microcode word required to implement the JUMP instruction).

JUMP Literal

BRANCH Literal

BEQZ Literal

BNEG Literal

JREG RS

LD RD Address

LDL RD Literal

LDX RD Address(RS)

ST Address RS

STX Address(RS2) RS1

ADD RD RS1 RS2

SUB, AND, OR and XOR are to work in exactly the same way, using the appropriate ALU function code (1, 2, 3, 4, respectively).

ADDL RD RS Literal

SUBL, ANDL, ORL and XORL are to work in exactly the same way, using the appropriate ALU function code (1, 2, 3, 4, respectively).

SLL RD RS1 RS2

SRL (Shift Right Logical) and SRA (Shift Right arithmetic) are to work in exactly the same way, using the appropriate ALU function code (6, 7, respectively); SRA copies the sign digit into digits to its left, SRL inserts zeros.

SLLL RD RS Literal

SRLL and SRAL are to work in exactly the same way, using the appropriate ALU function code (6, 7, respectively).

MUL RD RS1 RS2 / MULL RD RS Literal

DIV RD RS1 RS2 / DIVL RD RS Literal

OP1 and OP2

STOP

EMMA-3 Microinstruction Formats

Microcode Unit Control Fields

The Microcode Unit has two inputs, four data outputs and control signal outputs to the PC unit, the Data Memory, the Registers and the ALU (to avoid screen clutter, the control outputs are not all shown separately). The Address or Literal (Immediate) field of the instruction in IR can be sent to BUS1 or BUS2, and the address field of the current microcode word (CW) can be sent to the Microprogram Counter. The Microcode Unit can also output the integer value +1 to BUS2. This could be used in, for example, the implementation of a Load & Decrement instruction.

The bits in the second field select the ALU condition code (~CC0 or CC1) and determine whether the microcode subfield destined for the Microprogram Counter, the Program Counter, the Registers, the Data Memory or the ALU is sent or not according in one case to whether the condition is satisfied and the other case according to whether the condition is not satisfied. This facility can be used to implement conditional branch instructions (BNEG, BNEZ) and to implement loops within the microcode. The MICROCODE UNIT reads CC0 and CC1 directly from the ALU and can use them in condition tests in the clock period immediately following a clock period in which it initiates an ALU operation.

Microprogram Counter & Program Counter Control Fields

Registers Control Field

Data Memory Control Field (M-Format)

ALU Control Fields (M-Format)

ALU Control Fields (A-Format)

ALU Functions

Function E also takes the Operand in the microinstruction as its argument. The counter D is set at the start of a divide operation to count the number of cycles (17 for the simplest algorithm).

Microcode Timing

Figure 2 Microcode Timing Diagram

If the instruction requires more than two microcode words, MPC must be incremented once for each additional word and, for every instruction, the last microinstruction to be executed must update PC. Except in the case of a branch or jump instruction, PC must be incremented by +1. In the case of a conditional branch, then depending on the outcome, a new instruction can arrive in IR at the same time as a new microinstruction. As noted earlier, this can happen during the execution of branch instructions and if it does, a statement to this effect appears in the Output Pane of the HASE window and the new microinstriction is simply ignored.

It is important to remember that when an ALU operation is initiated, the Condition Code bits should not be selected for use in a conditional operation until the clock period after the ALU operation has completed.

Using the Model

The Data Memory contains values in each of its first 32 locations equal to their address. The assembly code contained in the Instruction Memory consists of just two instructions:

LD R2 5   // Loads R2 from data memory word 5
STOP       // Stops the simulation

To add additional microcode and assembly code to the model, edit the files called MICROCODE.Microcode.mem and I_MEMORY.Instructions.mem. Then reload the model, re-run the simulation and watch what happens. When a simulation is run, the Output Pane of the HASE window records, for each clock cycle, the current Microcode Memory address and the codeword being processed. Sometimes this will be different from the codeword at that address because it is overridden by zeros in a branch slot.

Suggested Exercises

1. Using only M-Format microinstructions, implement the remaining microcode for instructions 0 - 25 and write an appropriate assembly code program to demonstrate that they work.

2. Using A-Format microinstructions, implement the multiply and divide instructions and demonstrate that they work on suitable test data, including all possible combinations of positive and negative numbers. The microcode for divide the operations should stop the simulation if an attempt is made to divide by zero.

3. Implement OP1 and OP2 with functions of your own choice and demonstrate that they work on suitable test data. An example might be to form the sum of the first n natural numbers, where n is the number in RS1 and the result is stored in RD. Expect RS1 to be zero at the end of the operation.

Multiplication

Since the result of a multiply operation must not exceed 32 bits and since the divide algorithm described below will only work with 16-bit numbers, then whenever the ALU receives new operands for a multiply or divide operation (as indicated by a boolean variable set in the Microcode Unit), it checks its input values and stops the simulation if one or other is out of range. Literal values are automatically truncated to be in range, so these checks only matter for variables read from the Data Memory.

Division

This algorithm only works for 16-bit positive numbers. The ALU checks its input values and stops the simulation if they are out of range. If either value is negative, it must be negated at the start and the result negated, if appropriate, at the end. It’s also essential that the microcode stops the simulation (by jumping to location 255) if an attempt is to made to divide by zero.

Hints

• You will find it helps to use the Label field as exemplified in the figure, i.e. in the jump table section the label identifies the function whose numerical value corresponds to that address and in the remainder of the microcode memory the label is either the address of the location or the name of the instruction whose microcode starts at that location. You can download microcode design sheets in html or pdf format.

• All fields in the microcode word (Label, Microcode, Operand) must be filled.

• During development, some forms of error in the microcode can lead to the simulation running for ever (as can forgetting the STOP instruction at the end of the assembly code program). To prevent this happening, the Microcode unit checks the current clock number against the value of max_cycles and stops the simulation if it is exceeded. max_cycles is set at the beginning of each simulation by the statement max_cycles = 1 << log_max_cycles; where log_max_cycles is a RANGE parameter set in the .edl file with a range of 1-20 and an initial value of 11. To change this value, adjust the slider as required before starting a simulation, then update the .params file by clicking the parameters update icon in the top row of icons in the HASE window.

• When implementing MUL and DIV, it is helpful to draw flowcharts before microcoding to show how the microcode will deal with positive and negative values and in the case of DIV, a zero denominator.

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