Bluespec, Inc. provides tools for chip design (ASICs and FPGAs) that draw much inspiration from Term Rewriting Systems and Haskell. Bluespec also uses Haskell to implement many of its tools.

Bluespec's products include synthesis, simulation and other tools for two languages:

Both languages are based on a common semantic model: hardware behavior is expressed using Rewrite Rules, and inter-module communication is expressed using Rule-based Interface Methods (which allow rules to be composed from fragments that span module boundaries). Because rules are atomic, they eliminate a majority of the "timing errors" and "race conditions" that plague current hardware design using existing RTL languages like Verilog or VHDL. Rules also enable powerful reasoning about the functional correctness of systems. In other words, the concurrency model provided by rules is much more powerful and abstract than the low-level concurrency models provided by Verilog, VHDL and SystemC.

BSV incorporates Haskell-style polymorphism and overloading (typeclasses) into SystemVerilog's type system. BSV also treats modules, interfaces, rules, etc. as first-class objects, permitting very powerful static elaboration (including recursion).

Bluespec tools synthesize rules into clocked synchronous hardware descriptions (in Verilog RTL) that can be simulated or further synthesized to netlists using industry standard tools. This automates the generation of control logic to manage complex concurrent state update, a major source of errors in current design methodology where this logic must be manually coded by the designer.

Bluespec is a member of standards committees like IEEE P1800 (SystemVerilog) and IEEE P1666 (SystemC), where it tries to encourage adoption of the declarative programming ideas in BSV and ESE. The constructs for "tagged unions (algebraic types) and pattern matching" in the current IEEE SystemVerilog standard were contributed by Bluespec.