Publications

A comprehensive list of my papers, books and patents can be found on Google Scholar.

  1. 1985
  2. MU6V: A Parallel Vector Processing System, Ibbett, R. N., Capon, P. C. & Topham, N. P. 1985 Proceedings of the 12th Annual International Symposium on Computer Architecture. Los Alamitos, CA, USA: IEEE Computer Society Press, p. 136-144 9 p. (ISCA '85)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  3. 1987
  4. Performance Analysis of a Data-driven Multiple Vector Processing System, Topham, N. P. 1987 Proceedings of the IFIP WG 10.3 Working Conference on Highly Parallel Computers for Numerical and Signal Processing Applications on Highly Parallel Computers. New York, NY, USA: Elsevier North-Holland, Inc., p. 111-125 15 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  5. Context flow: An alternative to conventional pipelined architectures, Topham, N., Omondi, A. & Ibbett, R. 1988 In : Journal of Supercomputing. 2, 1, p. 29-53 25 p.

    Research output: Contribution to journal \u203a Article

  6. On the design and performance of conventional pipelined architectures, Topham, N., Omondi, A. & Ibbett, R. 1988 In : Journal of Supercomputing. 1, 4, p. 353-393 41 p.

    Research output: Contribution to journal \u203a Article

  7. 1989
  8. Array Processor Software, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 67-82 16 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  9. Array-processor Architecture, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 6-21 16 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  10. Instruction Buffers, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 74-95 22 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  11. Instructions and Addresses, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 7-25 19 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  12. Interconnection Networks, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 22-42 21 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  13. Message-passing Multiprocessors, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 141-167 27 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  14. Multiprocessor Architecture, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 83-108 26 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  15. Multiprocessor Software, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 169-193 25 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  16. Performance of Vector Machines, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 180-192 13 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  17. Pipelines, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 49-73 25 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  18. Practical Array Architectures, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 43-66 24 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  19. Shared-memory Multiprocessors, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems. New York, NY: Springer New York, p. 109-140 32 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  20. Storage Hierarchies, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 26-48 23 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  21. The Architecture of High Performance Computers, Vol.1, Ibbett, R. N. & Topham, N. P. 1989 Palgrave Macmillian. 200 p.

    Research output: Book/Report \u203a Book

  22. The Architecture of High Performance Computers, Vol.2, Ibbett, R. N. & Topham, N. P. 1989 Palgrave Macmillian. 209 p.

    Research output: Book/Report \u203a Book

  23. The CDC Series, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I Uniprocessors and vector processors. Springer New York, p. 156-179 24 p. Chapter 9

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  24. The CRAY Series, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I Uniprocessors and vector processors. New York, NY: Springer New York, p. 113-139 27 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  25. Vector Facilities in MU5, Ibbett, R. N. & Topham, N. P. 1989 Architecture of High Performance Computers: Volume I: Uniprocessors and vector processors. London: Macmillan Education UK, p. 140-155 16 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  26. 1990
  27. A general bound on schedule length for independent tasks, Manoharan, S. & Topham, N. P. 1990 In : Parallel Computing. 16, 1, p. 69-73 5 p.

    Research output: Contribution to journal \u203a Article

  28. 1992
  29. A Comparison of Two Memory Systems for High Performance Computers, Bird, P. L., Topham, N. P. & Manoharan, S. 1992 Proceedings of CONPAR `92. Springer-Verlag, p. 399-404 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  30. A comparison of two memory models for high performance computers, Bird, P. L., Topham, N. P. & Manoharan, S. 1992 Parallel Processing: CONPAR 92\u2014VAPP V: Second Joint International Conference on Vector and Parallel Processing Lyon, France, September 1\u20134, 1992 Proceedings. Bougé, L., Cosnard, M., Robert, Y. & Trystram, D. (eds.). Berlin, Heidelberg: Springer Berlin Heidelberg, p. 399-404 6 p. (Lecture Notes in Computer Science; vol. 634)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  31. Programming Environments for Parallel Computing: Proceedings of IFIP WG 10.5 Workshop on Programming Environments for Parallel Computing, Topham, N. P. (ed.), Ibbett, R. N. (ed.) & Bemmerl, T. (ed.) 1992 North-Holland Publishing Company. 244 p. (IFIP Transactions)

    Research output: Book/Report \u203a Book

  32. Semantics Driven Computer Architecture, Bird, P. L., Pleban, U. F., Topham, N. P. & Scheuer, H. Sep 1992 Proceedings of International Conference on Parallel Computing. p. 267-274 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  33. 1993
  34. Performance of Weak Consistency Schemes on the DEC Alpha, Harris, T. & Topham, N. P. 1993 Parallel Computing: Trends and Applications, PARCO 1993, Grenoble, France. p. 429-436 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  35. The Effectiveness of Decoupling, Bird, P. L., Rawsthorne, A. & Topham, N. P. 1993 Proceedings of the 7th International Conference on Supercomputing. New York, NY, USA: ACM, p. 47-56 10 p. (ICS '93)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  36. The Performance of Parallel Loops on SCI-Based Memory Hierarchies, Hexsel, R. A. & Topham, N. P. 1993 Parallel Computing: Trends and Applications, PARCO 1993, Grenoble, France. p. 703-706 4 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  37. 1994
  38. The Performance of SCI Memory Hierarchies, Hexsel, R. A. & Topham, N. P. 1994 Proceedings of Int. Workshop on Large-Scale Shared Memory Systems. IEEE Press, 17 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  39. Trace-driven simulation of decoupled architectures, Manoharan, S., Topham, N. P. & Crawford, A. W. R. 4 Jan 1994 System Sciences, 1994. Proceedings of the Twenty-Seventh Hawaii International Conference on. Vol. 1, p. 271-278 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  40. The Use of Caching in Decoupled Multiprocessors with Shared Memory, Harris, T. J. & Topham, N. P. Apr 1994 Proceedings of Int. Workshop on Large-Scale Shared Memory Systems. IEEE Press, 16 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  41. The scalability of decoupled multiprocessors, Harris, T. J. & Topham, N. P. 1 May 1994 Scalable High-Performance Computing Conference, 1994., Proceedings of the. p. 17-22 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  42. 1995
  43. Compiling and Optimizing for Decoupled Architectures, Topham, N., Rawsthorne, A., McLean, C., Mewissen, M. & Bird, P. 1995 Supercomputing, 1995. Proceedings of the IEEE/ACM SC95 Conference. IEEE Press, p. 40-40 1 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  44. Performance of the decoupled ACRI-1 architecture: The perfect club, Topham, N. & McDougall, K. 1995 High-Performance Computing and Networking: International Conference and Exhibition Milan, Italy, May 3\u20135, 1995 Proceedings. Hertzberger, B. & Serazzi, G. (eds.). Springer Berlin Heidelberg, p. 472-480 9 p. (Lecture Notes in Computer Science; vol. 919)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  45. An Assessment of Assignment Schemes for Dependency Graphs, Manoharan, S. & Topham, N. P. 1 Jan 1995 In : Parallel Computing. 21, 1, p. 85-107 23 p.

    Research output: Contribution to journal \u203a Article

  46. The Performance of SCI Multiprocessor Rings, Hexsel, R. A. & Topham, N. P. Jul 1995 In : The Journal of the Brazilian Computer Society. 1, 2, p. 24-37 14 p.

    Research output: Contribution to journal \u203a Article

  47. 1996
  48. The Performance of Cache Coherency in SCI-based Multiprocessors, Hexsel, R. A. & Topham, N. P. 1996 Proceedings of VIII Simp. Brasileiro de Arquitetura de Computadores e Processamento de Alto Desempenho (SBAC-PAD '96). p. 47-56 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  49. 1997
  50. A limitation study into access decoupling, Jones, G. P. & Topham, N. P. 1997 Euro-Par'97 Parallel Processing: Third International Euro-Par Conference Passau, Germany, August 26\u201329, 1997 Proceedings. Lengauer, C., Griebl, M. & Gorlatch, S. (eds.). Springer Berlin Heidelberg, p. 1102-1111 10 p. (Lecture Notes in Computer Science; vol. 1300)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  51. Allocating Lifetimes to Queues in Software Pipelined Architectures, Fernandes, M. M., Llosa, J. & Topham, N. P. 1997 Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings. Springer Berlin Heidelberg, p. 1066-1073 8 p. (Lecture Notes in Computer Science)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  52. Eliminating Cache Conflict Misses Through XOR-based Placement Functions, González, A., Valero, M., Topham, N. & Parcerisa, J. M. 1997 Proceedings of the 11th International Conference on Supercomputing. New York, NY, USA: ACM, p. 76-83 8 p. (ICS '97)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  53. The Effect of Restricted Instruction Issue Width on an Access Decoupled Architecture, Jones, G. P. & Topham, N. P. 1997 Parallel Computing: Fundamentals, Applications and New Directions, Proceedings of the Conference ParCo'97, 19-22 September 1997, Bonn, Germany.. p. 665-672 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  54. A comparison of data prefetching on an access decoupled and superscalar machine, Jones, G. P. & Topham, N. P. 1 Dec 1997 Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on. p. 65-70 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  55. The design and performance of a conflict-avoiding cache, Topham, N., Gonzalez, A. & Gonzalez, J. 1 Dec 1997 Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on. p. 71-80 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  56. 1998
  57. Partitioned schedules for clustered VLIW architectures, Fernandes, M. M., Llosa, J. & Topham, N. 1 Mar 1998 Parallel Processing Symposium, 1998. IPPS/SPDP 1998. Proceedings of the First Merged International ... and Symposium on Parallel and Distributed Processing 1998. p. 386-391 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  58. 1999
  59. Distributed modulo scheduling, Fernandes, M. M., Llosa, J. & Topham, N. 1 Jan 1999 High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On. p. 130-134 5 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  60. Randomized Cache Placement for Eliminating Conflicts, Topham, N. & González, A. 1 Feb 1999 In : IEEE Transactions on Computers. 48, 2, p. 185-192 8 p.

    Research output: Contribution to journal \u203a Article

  61. 2000
  62. Multiple-banked Register File Architectures, Cruz, J-L., González, A., Valero, M. & Topham, N. P. 2000 Proceedings of the 27th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, p. 316-325 10 p. (ISCA '00)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  63. 2002
  64. OneDSP: A unifying DSP architecture for Systems-on-a-Chip, Wong, K-L. & Topham, N. 1 May 2002 Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on. Vol. 4, p. IV-3792-IV-3795 4 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  65. Handling of loops in processors, Topham, N. & Livesley, R. 1 Oct 2002

    Research output: Patent

  66. Address translation, Topham, N. & Lim, S. 3 Oct 2002 30 Mar 2001

    Research output: Patent

  67. 2003
  68. High performance IDCT realization using complex arithmetic, Wong, K-L. & Topham, N. 1 Apr 2003 Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on. Vol. 2, p. II-313-16 vol.2 4 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  69. 2004
  70. Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit, Topham, N. 2004

    Research output: Patent

  71. Register File Circuitry, Topham, N. 2004

    Research output: Patent

  72. Renaming Registers to Values Produced by Instructions According to Assigned Produce Sequence Number, Topham, N. 2004

    Research output: Patent

  73. 2005
  74. Predicated Execution of Instructions in Processors, Topham, N. 2005

    Research output: Patent

  75. Early resolving instructions, Joyce, N. & Topham, N. 1 Feb 2005

    Research output: Patent

  76. Barrel shifter for a microprocessor, Wong, K. L. & Topham, N. 1 Dec 2005

    Research output: Patent

  77. Systems and methods for performing branch prediction in a variable length instruction set microprocessor, Wong, K. L., Hakewill, J., Topham, N. & Fuhler, R. 1 Dec 2005

    Research output: Patent

  78. 2006
  79. Challenges to Automatic Customization, Topham, N. P. 2006 Customizable Embedded Processors: Design Technologies and Applications. Lenne, P. & Leupers, R. (eds.). Morgan Kaufman, p. 185-208 24 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter

  80. Processor Adapted to Receive Different Instruction Sets, Topham, N. 2006

    Research output: Patent

  81. Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions, Topham, N. 2006

    Research output: Patent

  82. Stall Control, Topham, N. 2006

    Research output: Patent

  83. 2007
  84. A Hybrid Markov Model for Accurate Memory Reference Generation, Hassan, R., Harris, A., Topham, N. P. & Efthymiou, A. 2007 Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, March 21-23, 2007, Hong Kong, China. p. 550-555 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  85. Architecture for microprocessor-based systems including simd processing unit and associated systems and methods, Wong, K-L., Graham, C., Topham, N., Jones, S., Aristodemou, A., Nemouchi, Y. & Lim, S. C. 2007 WO 200704915028 Sep 2005

    Research output: Patent

  86. Parameterizable clip instruction and method of performing a clip operation using the same, Topham, N., Nemouchi, Y., Jones, S., Graham, C., Wong, K-L. & Aristodemou, A. 2007 28 Sep 2005

    Research output: Patent

  87. Work in Progress: On the Scalability of Storage Sub-system Back-end Network, Li, Y., Courtney, T., Ibbett, R. N. & Topham, N. 2007 Proceedings of the 5th USENIX Conference on File and Storage Technologies. Berkeley, CA, USA: USENIX Association, p. 7-7 1 p. (FAST '07)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  88. Work in Progress: Performance Evaluation of RAID6 Systems, Li, Y., Courtney, T., Ibbett, R. N. & Topham, N. P. 2007 WiP of FAST. 1 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  89. Systolic-array based systems and methods for performing block matching in motion compensation, Topham, N. 1 Mar 2007

    Research output: Patent

  90. Synthetic Trace-Driven Simulation of Cache Memory, Hassan, R., Harris, A., Topham, N. & Efthymiou, A. 1 May 2007 Advanced Information Networking and Applications Workshops, 2007, AINAW '07. 21st International Conference on. Vol. 1, p. 764-771 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  91. Combining Source-to-source Transformations and Processor Instruction Set Extensions for the Automated Design-space Exploration of Embedded Systems, Bennett, R. V., Murray, A. C., Franke, B. & Topham, N. 1 Jun 2007 LCTES '07 Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems. ACM, p. 83-92 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  92. 2008
  93. On The Scalability of Storage Sub-system Back-end Network, Li, Y., Courtney, T., Topham, N. P. & Ibbett, R. N. 2008 SPECTS 2008.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  94. Translating a simulation-target memory access to a simulation-host memory access, Topham, N. P. 1 May 2008

    Research output: Patent

  95. Resource Sharing in Custom Instruction Set Extensions, Zuluaga, M. & Topham, N. 1 Jun 2008 Application Specific Processors, 2008. SASP 2008. Symposium on. IEEE, p. 7-13 7 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  96. 2009
  97. An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection Based on GCC, Almer, O., Bennett, R., Böhm, I., Murray, A., Qu, X., Zuluaga, M., Franke, B. & Topham, N. P. 2009 GROW'09: Proceedings of the 1st International Workshop on GCC Research Opportunities. p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  98. High Speed CPU Simulation using LTU Dynamic Binary Translation, Jones, D. & Topham, N. P. 2009 4th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC). Springer Berlin Heidelberg, p. 50-64 15 p. (Lecture Notes in Computer Science)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  99. Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions, Zuluaga, M., Kluter, T., Brisk, P., Topham, N. P. & Ienne, P. 2009 SASP'09: Proceedings of the 7th IEEE Symposium on Application Specific Processors. p. 114-121 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  100. Code transformation and instruction set extension, Murray, A. C., Bennett, R. V., Franke, B. & Topham, N. 1 Jul 2009 In : ACM Transactions on Embedded Computing Systems. 8, 4, 31 p., 26

    Research output: Contribution to journal \u203a Article

  101. Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions, Zuluaga, M. & Topham, N. 1 Dec 2009 In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 12, p. 1788-1801 14 p.

    Research output: Contribution to journal \u203a Article

  102. 2010
  103. Adaptive High-Speed Processor Simulation, Topham, N., Franke, B., Jones, D. & Powell, D. 2010 Processor and System-on-Chip Simulation. Leupers, R. & Temam, O. (eds.). Springer US, p. 145-159 15 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Chapter (peer-reviewed)

  104. Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator, Bohm, I., Franke, B. & Topham, N. 1 Jul 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010). p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  105. Exploring the unified design-space of custom-instruction selection and resource sharing, Zuluaga, M. & Topham, N. 1 Jul 2010 Embedded Computer Systems (SAMOS), 2010 International Conference on. p. 282-291 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  106. 2011
  107. A Learning-Based Approach to the Automated Design of MPSoC Networks, Almer, O., Topham, N. & Franke, B. 2011 Architecture of Computing Systems - ARCS 2011: 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings. Berekovic, M., Fornaciari, W., Brinkschulte, U. & Silvano, C. (eds.). Springer-Verlag Berlin Heidelberg, p. 243-258 16 p. (Lecture Notes in Computer Science; vol. 6566)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  108. A Reconfigurable Cache Architecture for Energy Efficiency, Sundararajan, K. T., Jones, T. M. & Topham, N. 2011 Proceedings of the 8th ACM International Conference on Computing Frontiers. New York, NY, USA: ACM, p. 9:1-9:2 2 p. (CF '11)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  109. Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator, Bohm, I., Franke, B. & Topham, N. 2011 In : Transactions on High Performance and Embedded Architecture and Compilation. 5, 4, 20 p.

    Research output: Contribution to journal \u203a Article

  110. Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator, Bohm, I., Edler von Koch, T. J. K., Kyle, S. C. ., Franke, B. & Topham, N. 2011 Proceedings of the 32nd ACM SIGPLAN conference on Programming Language Design and Implementation (PLDI '11). New York, NY, USA: ACM, p. 74-85 12 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  111. Selecting the optimal system: automated design of application-specific systems-on-chip, Almer, O., Gould, M., Topham, N. & Franke, B. 2011 Proceedings of the 4th International Workshop on Network on Chip Architectures - NoCArc 2011. ACM, p. 43-50

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  112. The EnCore Microprocessor, Topham, N. 2011

    Research output: Non-textual form \u203a Artefact

  113. Virtual Manycore platforms: Moving towards 100 #x002B; processor cores, Leupers, R., Eeckhout, L., Martin, G., Schirrmeister, F., Topham, N. & Chen, X. 1 Mar 2011 Design, Automation Test in Europe Conference Exhibition (DATE), 2011. IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  114. Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency, Sundararajan, K. T., Jones, T. M. & Topham, N. 1 Jul 2011 Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'11). p. 41-50 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  115. Scalable multi-core simulation using parallel dynamic binary translation, Almer, O., Böhm, I., Von Koch, T. E., Franke, B., Kyle, S., Seeker, V., Thompson, C. & Topham, N. 7 Nov 2011 Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011. p. 190-199 10 p. 6045461

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  116. 2012
  117. Design Space Exploration of Hybrid Ultra Low Power Branch Predictors, Bielby, M., Gould, M. & Topham, N. 2012 Architecture of Computing Systems \u2013 ARCS 2012: 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings. SpringerLink, Vol. 7179, p. 184-199 (Lecture Notes in Computer Science; vol. 7179)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  118. Efficiently Parallelizing Instruction Set Simulation of Embedded Multi-core Processors Using Region-based Just-in-time Dynamic Binary Translation, Kyle, S., Böhm, I., Franke, B., Leather, H. & Topham, N. 2012 Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems. New York, NY, USA: ACM, p. 21-30 10 p. (LCTES '12)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  119. Energy-efficient Cache Partitioning for Future CMPs, Sundararajan, K. T., Jones, T. M. & Topham, N. P. 2012 Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. New York, NY, USA: ACM, p. 465-466 2 p. (PACT '12)

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  120. Predicting best design trade-offs: a case study in processor customization, Zuluaga, M., Bonilla, E. & Topham, N. 2012 Proceedings of the Conference on Design, Automation and Test in Europe. San Jose, CA, USA: EDA Consortium, p. 1030-1035 6 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  121. Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs, Sundararajan, K. T., Porpodas, V., Jones, T. M., Topham, N. P. & Franke, B. 1 Feb 2012 High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on. IEEE COMPUTER SOC, p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  122. 2013
  123. Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description, Gould, M., Wagstaff, H., Franke, B. & Topham, N. 2013 Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013. ACM, 21

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  124. A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation, Almer, O., Boehm, I., von Koch, T. E., Franke, B., Kyle, S., Seeker, V., Thompson, C. & Topham, N. Apr 2013 In : International journal of parallel programming. 41, 2, p. 212-235 24 p.

    Research output: Contribution to journal \u203a Article

  125. The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation, Sundararajan, K. T., Jones, T. M. & Topham, N. P. Apr 2013 In : International journal of parallel programming. 41, 2, p. 305-330 26 p.

    Research output: Contribution to journal \u203a Article

  126. High speed cycle approximate simulation for cache-incoherent MPSoCs, Gould, M., Thompson, C. & Topham, N. Jul 2013 Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on. IEEE, p. 88 - 95

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  127. RECAP: Region-Aware Cache Partitioning, Sundararajan, K. T., Jones, T. M. & Topham, N. P. Oct 2013 Computer Design (ICCD), 2013 IEEE 31st International Conference on. IEEE, p. 294-301 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  128. 2014
  129. Efficient Code Generation in a Region-based Dynamic Binary Translator, Spink, T., Wagstaff, H., Franke, B. & Topham, N. 2014 Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems. New York, NY, USA: ACM, p. 3-12 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  130. 2015
  131. Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator, Spink, T., Wagstaff, H., Franke, B. & Topham, N. 2015 Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. IEEE, p. 103 - 112 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  132. Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM, Nardi, L., Bodin, B., Zia, M. Z., Mawer, J., Nisbet, A., Kelly, P. H. J., Davison, A. J., Luján, M., O'Boyle, M. F. P., Riley, G., Topham, N. & Furber, S. 2015 IEEE Intl. Conf. on Robotics and Automation (ICRA 2015). IEEE, 8 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  133. 2016
  134. Characterizing memory bottlenecks in GPGPU workloads, Dublish, S., Nagarajan, V. & Topham, N. 10 Oct 2016 2016 IEEE International Symposium on Workload Characterization (IISWC). Providence, RI, USA: IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  135. Cooperative Caching for GPUs, Dublish, S., Nagarajan, V. & Topham, N. 1 Dec 2016 In : ACM Transactions on Architecture and Code Optimization. 13, 4, p. 1-25 25 p., 39

    Research output: Contribution to journal \u203a Article

  136. 2017
  137. Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs, Dublish, S., Nagarajan, V. & Topham, N. 13 Jul 2017 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, p. 239-248 10 p.

    Research output: Chapter in Book/Report/Conference proceeding \u203a Conference contribution

  138. 2018
  139. High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors, Thompson, C., Gould, M. & Topham, N. 26 Mar 2018 In : International journal of parallel programming. 36 p.

    Research output: Contribution to journal \u203a Article


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