Publications

A comprehensive list of my papers, books and patents can be found on Google Scholar.

A list of papers scraped from Edinburgh Research Explorer

    Papers in Journals and Conference Proceedings

  1. M. Zuluaga, T. Kluter, P. Brisk, N.P. Topham and P. Ienne, ``Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions'', to appear in IEEE Symposium on Application Specific Processors (SASP-2009), San Francisco, CA, July 2009.

  2. M. Zuluaga and N.P. Topham, ``Design Exploration of Resource Sharing Solutions for Custom Instruction Set Extensions'', to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

  3. R.V. Bennett, A.C. Murray, B. Franke and N.P. Topham, ``Code Transformation and Instruction Set Extension'', to appear in ACM Transactions on Embedded Computer Systems.

  4. O. Almer, R.V. Bennett, I Bohm, A.C. Murray, X. Qu, M. Zuluaga, B. Franke, and N.P. Topham, ``An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection based on GCC'', Proc. 1st International Workshop on GCC Research Opportunities (GROW'09), Paphos, Cyprus, 2009.

  5. D. Jones and N.P. Topham, ``High Speed CPU Simulation using LTU Dynamic Binary Translation'', Proc. 4th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Paphos, Cyprus, January 25-28, 2009.

  6. M. Zuluaga and N.P. Topham, ``Resource Sharing in Custom Instruction Set Extensions'', IEEE Symposium on Application Specific Processors (SASP-2008), Anaheim, CA, June 2008. (PDF).

  7. Y. Li, T. Courtney, R.N. Ibbett and N.P. Topham, ``On The Scalability of Storage Sub-system Back-end Network", in SPECTS 2008, Edinburgh, UK, 2008.

  8. R.V. Bennett, A.C. Murray, B. Franke and N.P. Topham, ``Combining Source-to-Source Transformations and Processor Instruction Set Extensions for the Automated Design-Space Exploration of Embedded Systems'', ACM SIGPLAN/SIGBED 2007 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego CA, June 2007. ACM portal.

  9. N.P. Topham and D. Jones, ``High Speed CPU Simulation using JIT Binary Translation'', 3rd Annual Workshop on Modeling, Benchmarking and Simulation, held in conjunction with ISCA-34, San Diego CA, June 2007.

  10. Y. Li, T. Courtney, R.N. Ibbett and N.P. Topham, ``Work in Progress: On the Scalability of Storage Sub-system Back-end Network", WiP of FAST, San Jose, USA, 2007.

  11. Y. Li, T. Courtney, R.N. Ibbett and N.P. Topham, ``Work in Progress: Performance Evaluation of RAID6 Systems", WiP of FAST, San Jose, USA, 2007.

  12. R. Hassan, A. Harris, N.P. Topham and A. Efthymiou, ``Synthetic Trace-Driven Simulation of Cache Memory'', The 4th IEEE International Symposium on Embedded Computing (SEC-07), Niagara Falls, Canada, May 2007.

  13. R. Hassan, A. Harris, N.P. Topham and A. Efthymiou, ``A Hybrid Markov Model for Accurate Memory Reference Generation'', IAENG Int. Conf. on Computer Science (ICCS'07), Hong Kong, Mar. 2007. Best student paper award.

  14. N.P. Topham, ``Challenges to Automatic Customization'', in Customizable Embedded Processors: Design Technologies and Applications, Paolo Ienne and Rainer Leupers (eds), Morgan Kaufman, July 2006, ISBN 0123695260.

  15. N.P. Topham and K.L. Wong, ``High Performance IDCT Realization using Complex Arithmetic'', Int. Conf. on Acoustic Speech and Signal Processing (ICASSP 2003), Hong Kong, June 2003.

  16. K.L. Wong and N.P. Topham, ``OneDSP - A Unifying DSP Architecture for Systems on a Chip'', Int. Conf. on Acoustic Speech and Signal Processing (ICASSP 2002), Orlando Fl., May 2002.

  17. J.L. Cruz, A. Gonzalez, M. Valero and N.P. Topham, ``Multiple-banked Register File Architectures'', 27th Annual IEEE/ACM Int. Symp. on Computer Architecture (ISCA-27), Vancouver, June 2000.

  18. N.P. Topham and A. Gonzalez, ``Randomized Cache Placement for Eliminating Conflicts'', IEEE Transactions on Computers, Feb. 1999.

  19. M. Fernandes, N.P. Topham and J. Llosa, ``Distributed Modulo Scheduling'', 5th Annual Int. IEEE Conf. on High Performance Computer Architecture (HPCA-5), Orlando, Fl., Jan. 1999.

  20. M. Fernandes, J. Llosa and N.P. Topham, ``Partitioned Schedules for Clustered VLIW Architectures'', IEEE/ACM Int. Parallel Processing Symposium, 1998.

  21. N.P. Topham, A. Gonzalez and J. Gonzalez, ``The Design and Performance of a Conflict-avoiding Cache'', 30th Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO-30), December 1997. (PDF).

  22. G. Jones and N.P. Topham, ``A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine'', 30th Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO-30), December 1997. (PDF).

  23. G. Jones and N.P. Topham, ``The Effect of Restricted Instruction Issue on Access Decoupled Architecture'', Proceedings of ParCo'97, Sept. 1997.

  24. M. Fernandes, J. Llosa and N.P. Topham, ``Using Queues for Register File Organization in VLIW Architectures'', Proc. EuroPar `97 , pp.1066-1073, Springer-Verlag, August 1997. (PDF).

  25. G. Jones and N.P. Topham, ``The Limits to Decoupling'', Proc. EuroPar `97 , pp.1102-1111, Springer-Verlag, August 1997. (PDF).

  26. A. Gonzalez, M. Valero, N.P. Topham and J.M. Parcerisa, ``Eliminating Cache Conflict Misses Through XOR-Based Placement Functions'', Proc. Int. Conf. Supercomputing `97 , Vienna (July, 1997)
    (PDF, 8 pgs, 24k).

  27. R.A. Hexsel and N.P. Topham, ``The Performance of Cache Coherency in SCI-based Multiprocessors'', Proc. VIII Simp. Brasileiro de Arquitetura de Computadores e Processamento de Alto Desempenho - SBAC-PAD '96, August 1996. ( PDF+gzip, 12 pgs, 78k)

  28. N.P. Topham, A. Rawsthorne, C.E. McLean, M.J.R.G. Mewissen, P. Bird, ``Compiling and Optimizing for Decoupled Architectures'', Proc. Supercomputing `95, San Diego (December, 1995), ACM Press.
    (also available as a single tar file, 67k)

  29. R.A. Hexsel and N.P. Topham, ``The Performance of SCI Multiprocessor Rings'', Journal of Brazilian Computer Society, July 1995. ( PDF, 56k)

  30. N.P. Topham and K. McDougall, ``Performance of the Decoupled ACRI-1 Architecture: the Perfect Club'', Proc. HPCN - Europe, Milan (May, 1995), LNCS 919, Springer-Verlag, pp.472-480.
    (a PDF version is also available)

  31. S. Manoharan and N.P. Topham, ``An Assessment of Assignment Schemes for Dependency Graphs'', Parallel Computing 21 (1995) pp.85-107.

  32. T.J. Harris and N.P. Topham, ``The Scalability of Decoupled Multiprocessors'', Proc. Scalable High Performance Computing Conference, Knoxville, TN, May 1994, IEEE Press. (a PDF version is available)

  33. R.A. Hexsel and N.P Topham, ``The Performance of SCI Memory Hierarchies'', Technical Report CSR-30-94, Department of Computer Science, University of Edinburgh, 1994. (a PDF version is available)

  34. R.A. Hexsel and N.P. Topham, ``The Performance of SCI Memory Hierarchies'', Proc. Int. Workshop on Large-Scale Shared Memory Systems, Cancun, Mexico, April 1994, IEEE Press.

  35. T.J., Harris and N.P. Topham, ``The Use of Caching in Decoupled Multiprocessors with Shared Memory'', Technical Report ECS-CSG-5-94, Department of Computer Science, University of Edinburgh, 1994. (a PDF version is available)

  36. T.J., Harris and N.P. Topham, ``The Use of Caching in Decoupled Multiprocessors with Shared Memory'', Proc. Int. Workshop on Large-Scale Shared Memory Systems, Cancun, Mexico, April 1994, IEEE Press.

  37. S. Manoharan, A.W.R.C. Crawford and N.P. Topham, ``Trace-Driven Simulation of Decoupled Architectures'', Proc. 27th Hawaiian International Conference on System Sciences, Maui, Hawaii, January 1994.

  38. R.A. Hexsel and N.P. Topham, ``The Performance of Parallel Loops on SCI-based Memory Hierarchies'', in Advances in Parallel Computing 9: trends and Applications, G.R. Joubert et al. (eds.), North Holland publishers, 1994.

  39. T.J. Harris and N.P. Topham, ``Performance of Weak Consistency Schemes on the DEC Alpha'', in Advances in Parallel Computing 9: trends and Applications, G.R. Joubert et al. (eds.), North Holland publishers, 1994. (a PDF version is available)

  40. P.L. Bird, A. Rawsthorne, and N.P. Topham, ``The Effectiveness of Decoupling'', in Proc. International ACM Conference on Supercomputing `93, Tokyo, Japan, July 1993. (a PDF version is available)

  41. P.L. Bird, N.P. Topham, and S. Manoharan, ``A Comparison of Two Memory Systems for High Performance Computers'', in Proc. CONPAR `92, Springer-Verlag, September 1992.

  42. N.P Topham, R.N. Ibbett, and T. Bemmerl, (eds.), ``Programming Environments for Parallel Computing'', Proc. IFIP WG 10.5 Workshop on Programming Environments for Parallel Computing, Edinburgh, April 1992.

  43. P.L. Bird, U.F. Pleban, N.P. Topham and H. Scheuer, ``Semantics Driven Computer Architecture'', in Proc. International Conference on Parallel Computing, September 1991.

  44. S. Manoharan and N.P. Topham, ``A General Bound on Schedule Length for Independent Tasks'', Parallel Computing, 16 (1990), pp.67-73.

  45. R.N. Ibbett and N.P. Topham, The Architecture of High Performance Computers, Vol.2, MacMillan Computer Science Series (2nd Edition), 1989.

  46. R.N. Ibbett and N.P. Topham, The Architecture of High Performance Computers, Vol.1, MacMillan Computer Science Series (2nd Edition), 1989.

  47. N.P. Topham, A.R. Omondi and R.N. Ibbett, ``Context Flow: An Alternative to Conventional Pipelined Architectures'', the Journal of Supercomputing, Vol. 2, 1988, pp.29-53.

  48. N.P. Topham, A.R. Omondi and R.N. Ibbett, ``On the Design and Performance of Conventional Pipelined Architectures'', the Journal of Supercomputing, Vol. 1, 1988, pp.353-393.

  49. N.P. Topham, ``Performance Analysis of a Data-Driven Multiple Vector Processing System'', in G.L. Reigns and M.H. Barton (Eds.), ``Highly Parallel Computers'', North Holland, Amsterdam, pp.111-125, 1987.

  50. R.N. Ibbett, P.C. Capon and N.P. Topham, ``MU6-V: A Parallel Vector Processing System'', in Proc. 12th Annual International Symposium on Computer Architecture, pp.136-144, 1985.

    US Patents Granted

  51. N.P. Topham, Processor Adapted to Receive Different Instruction Sets, October 31, 2006, US patent no. 7,130,989.

  52. N.P. Topham, Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions, October 17, 2006, US patent no. 7,124,279.

  53. K.L. Wong and N.P. Topham, Stall Control, January 31, 2006, US patent no. 6,993,641.

  54. N.P. Topham, Predicated Execution of Instructions in Processors, September 13, 2005, US patent no. 6,944,853.

  55. N.P. Topham, Renaming Registers to Values Produced by Instructions According to Assigned Produce Sequence Number, November 30, 2004, US patent no. 6,826,677.

  56. N.P. Topham, Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit, June 22, 2004, US patent no. 6,754,806.

  57. J.M. Harris, A.P. Wise and N.P. Topham, Register File Circuitry, May 4, 2004, US patent no. 6,732,251.

    US Patents Published and Pending

  58. N.P. Topham, Y. Nemouchi, S. Jones, C.N. Graham, K.L. Wong, A. Aristodemou, Parameterizable clip instruction and method of performing a clip operation using the same, March 29, 2007, US patent application no. 20070074007.

  59. N.P. Topham, Systolic-array based systems and methods for performing block matching in motion compensation, March 29, 2007, US patent application no. 20070071101.

  60. K.L. Wong and N.P. Topham, Barrel Shifter for a Microprocessor, December 29, 2005, US patent application no. 20050289323.

  61. K.L. Wong, J. Hakewill, N.P. Topham and R. Fuhler, Systems and methods for performing branch prediction in a variable length instruction set microprocessor, December 15, 2005, US patent application no. 20050278517.

  62. N.P. Topham, Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions , June 9, 2005, US patent application no. 20050125633.

  63. N.P. Joyce and N.P. Topham, Early Resolving Instructions, February 10, 2005, US patent application no. 20050033941.

  64. N.P. Topham and R.M. Livesley, Handling of Loops in Processors, October 3, 2002, US patent application no. 20020144092.

  65. N.P. Topham and C.S. Lim, Address Translation, October 3, 2002, US patent application no. 20020144078.

    Worldwide Patents (WIPO) Published and Pending

  66. N.P. Topham, Translating a Simulation-target Memory Access to a Simulation-host Memory Access, May 5, 2008, WIPO publication no. WO/2008/053160.

  67. K.L Wong, C. Graham, N.P. Topham, S. Jones, A. Aristodemou, Y. Nemouchi, S.C. Lim, Architecture for Microprocessor-based Systems Including SIMD Processing Unit and Associated Systems and Methods, May 3, 2007, WIPO publication no. WO/2007/049150.


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