Instruction Buffers
The problem of the disparity between processing speed and main store
accessing rate affects both operand and instruction accessing. Both
must be supplied to the processor at a rate matching its execution
rate if the system is to operate efficiently. In the case of
instruction accessing, however, the problem is ameliorated both by the
fact that most instructions are obeyed sequentially and because each
word fetched from the main store normally contains several
instructions. Furthermore, with an interleaved store, successive
accesses for sequential instructions reference each stack in turn and
are not held up by cycle time effects. Thus store requests can be made
in advance of the corresponding instruction being required and the
replies buffered until they are needed for execution. This
pre-fetching technique is used in almost all high performance
pipelined processors.
A significant proportion of instructions cause
a control transfer (a branch or a jump), however, and
each such transfer requires a request to be made to the store for a
new sequence of instructions. Thus although the accessing rate for
instructions can normally be matched satisfactorily to the processing
rate, the access time for the first instruction of a new sequence can
result in a long delay to the processor. Techniques for overcoming
this problem rely on the fact that the cause of many control transfers
is a branch back from the end to the start of a loop of instructions,
and loop-catching buffers are incorporated into a number of
processors.
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